View MB91F467SAPMC-GSE2_4807205.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU MICROELECTRONICS DATA SHEET
DS07-16617-2E
32-bit Microcontroller
CMOS
FR60 MB91460S Series MB91F467SA
DESCRIPTION
MB91460S series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs. This series contains the LIN-USART, CAN and APIXfi controllers. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Microelectronics Limited.
FEATURES
1. FR60 CPU core
32-bit RISC, load/store architecture, five-stage pipeline 16-bit fixed-length instructions (basic instructions) Instruction execution speed: 1 instruction per cycle Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for embedded applications Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language Register interlock function: Facilitating assembly-language coding Built-in multiplier with instruction-level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles Interrupts (save PC/PS) : 6 cycles (16 priority levels) Harvard architecture enabling program access and data access to be performed simultaneously Instructions compatible with the FR family
For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright'2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.9
MB91460S Series
2. Internal peripheral resources
General-purpose ports : Maximum 133 ports DMAC (DMA Controller) Maximum of 5 channels able to operate simultaneously. 2 transfer sources (internal peripheral/software) Activation source can be selected using software. Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Transfer data size selectable from 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) A/D converter (successive approximation type) 10-bit resolution: 16 channels Conversion time: minimum 1 s External interrupt inputs : 16 channels Shares the CAN RX pin and I2C SDA pin Bit search module (for REALOS) Function to search from the MSB (most significant bit) for the position of the first 0 , 1 , or changed bit in a word LIN-USART (full duplex double buffer): 6 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator I2C bus interface (supports 400 kbps): 3 channels Master/slave transmission and reception Arbitration function, clock synchronization function CAN controller (C-CAN): 2 channels Maximum transfer speed: 1 Mbps 32 transmission/reception message buffers APIXfi controller APIXfi link (105Mbit / 6Mbit): 1 channel Automotive Interconnect links (5Mbit / 6Mbit): 2 links Sound generator : 1 channel Tone frequency : PWM frequency divide-by-two (reload value + 1) Alarm comparator : 1 channel Monitor external voltage Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) 16-bit PPG timer : 16 channels 16-bit PFM timer : 1 channel 16-bit reload timer: 8 channels 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) Input capture: 8 channels (operates in conjunction with the free-run timer) Output compare: 4 channels (operates in conjunction with the free-run timer) Up/Down counter: 4 channels (4 8-bit or 2 16 bit) Watchdog timer Real-time clock Low-power consumption modes : Sleep/stop mode function Low voltage detection circuit Clock monitor
2
DS07-16617-2E
MB91460S Series
Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. Clock modulator * Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator Main oscillator stabilization timer Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter Sub-oscillator stabilization timer Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter
3. Package and technology
Package : LQFP-176 CMOS 0.18 m technology Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) Operating temperature range: between 40 C and + 105 C * : The clock modulator is currently being evaluated and should not be used for other purpose than testing. Note APIXfi is a registered mark of INOVA Semiconductors GmbH
DS07-16617-2E
3
MB91460S Series
PRODUCT LINEUP
Feature
Max. core frequency (CLKB) Max. resource frequency (CLKP) Max. external bus freq. (CLKT) Max. CAN frequency (CLKCAN) Max. FlexRay frequency (SCLK) Technology Watchdog Watchdog (RC osc. based) Bit Search Reset input (INITX) Hardware Standby input (HSTX) Clock Modulator Clock Monitor Low Power Mode DMA MAC ( DSP) MMU/MPU
MB91V460A
80MHz 40MHz 40MHz 20MHz 0.35 m yes yes (disengageable) yes yes yes yes yes yes 5 ch no MPU (16 ch) 1)
MB91F467SA
100MHz 50MHz 50MHz 40MHz 0.18 m yes yes yes yes no yes yes yes 5 ch no MPU (8 ch) 1)
Flash Satellite Flash Flash Protection
Emulation SRAM 32bit read data -
1088 KByte no yes
D-RAM ID-RAM Flash-Cache (Instruction cache) Boot-ROM / BI-ROM
64 KByte 64 KByte 16 KByte 4 KByte fixed
32 KByte 32 KByte 8 KByte 4 KByte
RTC Free Running Timer ICU OCU Reload Timer PPG 16-bit PFM 16-bit Sound Generator Up/Down Counter (8/16-bit)
1 ch 8 ch 8 ch 8 ch 8 ch 16 ch 1 ch 1 ch 4 ch (8-bit) / 2 ch (16-bit)
1 ch 8 ch 8 ch 4 ch 8 ch 16 ch 1 ch 1 ch 4 ch (8-bit) / 2 ch (16-bit)
(Continued)
4
DS07-16617-2E
MB91460S Series
(Continued) Feature
C_CAN LIN-USART I2C (400k) APIX
fi
MB91V460A
6 ch (128msg) 4 ch + 4 ch FIFO + 8 ch 4 ch -
MB91F467SA
2 ch (32msg) 2 ch + 4 ch FIFO 3 ch 2ch (1ch physical)
FR external bus
yes (32bit addr, 32bit data)
yes (24bit addr, 16bit data)
External Interrupts NMI Interrupts
16 ch 1 ch
16 ch 1 ch
SMC LCD controller (40x4)
6 ch 1 ch
-
ADC (10 bit) Alarm Comparator
32 ch 2 ch
16 ch 1 ch
Supply Supervisor Clock Supervisor
yes yes
yes yes
Main clock oscillator Sub clock oscillator RC Oscillator PLL
4MHz 32kHz 100kHz x 20
4MHz 32kHz 100kHz / 2MHz x 25
DSU4 EDSU
yes yes (32 BP)
*1
yes (16 BP) *1
Supply Voltage Regulator Power Consumption Temperature Range (Ta)
3V / 5V yes n.a. 0..70 C
3V / 5V yes <1W -40..105 C
Package
BGA660
LQFP176
Power on to PLL run Flash Download Time
< 20 ms n.a.
< 20 ms < 30 sec (2M)
*1 : MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
DS07-16617-2E
5
MB91460S Series
6
1. MB91F467SA
PIN ASSIGNMENT
VSS5 P07_4/A4 P07_5/A5 P07_6/A6 P07_7/A7 P06_0/A8 P06_1/A9 P06_2/A10 P06_3/A11 P06_4/A12 P06_5/A13 P06_6/A14 P06_7/A15 P05_0/A16 P05_1/A17 P05_2/A18 P05_3/A19 P05_4/A20 P05_5/A21 P05_6/A22 P05_7/A23 VDD35 VSS5 P01_0/D16 P01_1/D17 P01_2/D18 P01_3/D19 P01_4/D20 P01_5/D21 P01_6/D22 P01_7/D23 P00_0/D24 P00_1/D25 P00_2/D26 P00_3/D27 P00_4/D28 P00_5/D29 P00_6/D30 P00_7/D31 P09_0/CSX0 P09_1/CSX1 P09_2/CSX2 P09_3/CSX3 VDD35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
LQFP-176
(TOP VIEW)
(FPT-176P-M07)
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VSS5 P10_0 / SYSCLK / /SYSCLK P10_1 / ASX P10_3 / WEX P08_0 / WRX0 P08_1 / WRX1 P08_4 / RDX P08_7 / RDY P24_7 / INT7 P24_6 / INT6 P24_5 / INT5 / SCL2 P24_4 / INT4 / SDA2 P24_3 / INT3 P24_2 / INT2 P24_1 / INT1 P20_0 / SIN2 / AIN0 P20_1 / SOT2 / BIN0 P20_2 / SCK2 / ZIN0 / CK2 P20_4 / SIN3 / AIN1 P20_5 / SOT3 / BIN1 P20_6 / SCK3 / ZIN1 / CK3 VDD5 VSS5 P23_0 / RX0 / INT8 P23_1 / TX0 P23_2 / RX1 / INT9 P23_3 / TX1 P16_7 / PPG15 / ATGX P16_6 / PPG14 / PFM P16_5 / PPG13 / SGO P16_4 / PPG12 / SGA P16_3 / PPG11 P16_2 / PPG10 P16_1 / PPG9 P16_0 / PPG8 P17_7 / PPG7 / TCKI1 P17_6 / PPG6 / TDA11 P17_5 / PPG5 / TDA10 P17_4 / PPG4 P17_3 / PPG3 P17_2 / PPG2 / RDA11 P17_1 / PPG1 / RDA10 P17_0 / PPG0 / RCK1 VDD5
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VDD35 P07_3/A3 P07_2/A2 P07_1/A1 P07_0/A0 P14_7/ICU7/TIN15/7/TTG31/23/15/7 P14_6/ICU6/TIN14/6/TTG30/22/14/6 P14_5/ICU5/TIN13/5/TTG29/21/13/5 P14_4/ICU4/TIN12/4/TTG28/20/12/4 P14_3/ICU3/TIN11/3/TTG27/19/11/3 P14_2/ICU2/TIN10/2/TTG26/18/10/2 P14_1/ICU1/TIN9/1/TTG25/17/9/1 P14_0/ICU0/TIN8/0/TTG24/16/8/0 P15_3/OCU3/TOT3 P15_2/OCU2/TOT2 P15_1/OCU1/TOT1 P15_0/OCU0/TOT0 P22_7/SCL1 P22_6/SDA1/INT15 P22_5/SCL0 P22_4/SDA0/INT14 VSS5 VDD5 P22_2/INT13 P22_0/INT12 P23_6/INT11 P23_4/INT10 P28_7/AN15/TCKI0 P28_6/AN14/TDA01 P28_5/AN13/TDA00 P28_4/AN12 P28_3/AN11 P28_2/AN10/RDA01 P28_1/AN9/RDA00 P28_0/AN8/RCK0 P29_7/AN7 P29_6/AN6 P29_5/AN5 P29_4/AN4 P29_3/AN3 P29_2/AN2 P29_1/AN1 P29_0/AN0 VSS5
VDD5 AVCC5 AVRH5 AVSS ALARM P18_6/SCK7/ZIN3/CK7 P18_5/SOT7/BIN3 P18_4/SIN7/AIN3 P18_2/SCK6/ZIN2/CK6 P18_1/SOT6/BIN2 P18_0/SIN6/AIN2 P19_6/SCK5/CK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4/CK4 P19_1/SOT4 P19_0/SIN4 P24_0/INT0 MD_2 MD_1 MD_0 VSS5 VDD5 VDD5R VDD5R VCC18C VSS5 VSSA VDDA SDOUTM SDOUTP SDINM SDINP VSSA NMIX INITX X1A X0A VSS5 X0 X1 MD_3 MONCLK VSS5
DS07-16617-2E
MB91460S Series
Pin no.
Pin name P24_4
I/O
I/O circuit type* C
Function General-purpose input/output port
56
INT4 SDA2 P24_3 INT3 P24_2 INT2 P24_1 INT1 P20_0 SIN2 AIN0 P20_1
I/O
External interrupt input pin I2C bus DATA input/output pin General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port Data input pin of USART2 Up/down counter input pin General-purpose input/output port
57 58 59
I/O I/O I/O
A A A
60
I/O
A
61
SOT2 BIN0 P20_2 SCK2 ZIN0 CK2 P20_4
I/O
A
Data output pin of USART2 Up/down counter input pin General-purpose input/output port Clock input/output pin of USART2 Up/down counter input pin External clock input pin of free-run timer 2 General-purpose input/output port
62
I/O
A
63
SIN3 AIN1 P20_5
I/O
A
Data input pin of USART3 Up/down counter input pin General-purpose input/output port
64
SOT3 BIN1 P20_6 SCK3 ZIN1 CK3 P23_0
I/O
A
Data output pin of USART3 Up/down counter input pin General-purpose input/output port Clock input/output pin of USART3 Up/down counter input pin External clock input pin of free-run timer 3 General-purpose input/output port
65
I/O
A
68
RX0 INT8 P23_1 TX0
I/O
A
RX input/output pin of CAN0 External interrupt input pin General-purpose input/output port TX output pin of CAN0 (Continued)
69
I/O
A
8
DS07-16617-2E
MB91460S Series
Pin no.
Pin name P17_5
I/O
I/O circuit type* A
Function General-purpose input/output port
82
PPG5 TDA10 P17_4 PPG4 P17_3 PPG3 P17_2 PPG2 RDA11 P17_1
I/O
Output pin of PPG timer AIC downlink data of Apixfi link1 General-purpose input/output port Output pin of PPG timer General-purpose input/output port Output pin of PPG timer General-purpose input/output port Output pin of PPG timer AIC uplink data of Apixfi link1 General-purpose input/output port
83 84
I/O I/O
A A
85
I/O
A
86
PPG1 RDA10 P17_0
I/O
A
Output pin of PPG timer AIC uplink data of Apixfi link1 General-purpose input/output port
87 90 91 92 93 95 96 97 98 100 101 102 103 112 to 114 115
PPG0 RCK1 MONCLK MD_3 X1 X0 X0A X1A INITX NMIX SDINP SDINM SDOUTP SDOUTM MD_0 to MD_2 P24_0 INT0
I/O O I
A M G00 J1 J1 J2 J2
Output pin of PPG timer AIC uplink clock of Apixfi link1 Clock monitor pin Fast clock input pin Clock (oscillation) output Clock (oscillation) input Sub clock (oscillation) input Sub clock (oscillation) output External reset input pin Non-maskable interrupt input pin Apixfi uplink Apixfi uplink Apixfi downlink Apixfi downlink Mode setting pins General-purpose input/output port External interrupt input pin (Continued)
I I
H H N1 N1 N2 N2
I I/O
G01 A
10
DS07-16617-2E
MB91460S Series
Pin no. 116 117
Pin name P19_0 SIN4 P19_1 SOT4 P19_2 SCK4 CK4 P19_4 SIN5 P19_5 SOT5 P19_6 SCK5 CK5 P18_0
I/O I/O I/O
I/O circuit type* A A
Function General-purpose input/output port Data input pin of USART4 General-purpose input/output port Data output pin of USART4 General-purpose input/output port Clock input/output pin of USART4 External clock input pin of free-run timer 4 General-purpose input/output port Data input pin of USART5 General-purpose input/output port Data output pin of USART5 General-purpose input/output port Clock input/output pin of USART5 External clock input pin of free-run timer 5 General-purpose input/output port
118
I/O
A
119 120
I/O I/O
A A
121
I/O
A
122
SIN6 AIN2 P18_1
I/O
A
Data input pin of USART6 Up/down counter input pin General-purpose input/output port
123
SOT6 BIN2 P18_2 SCK6 ZIN2 CK6 P18_4
I/O
A
Data output pin of USART6 Up/down counter input pin General-purpose input/output port Clock input/output pin of USART6 Up/down counter input pin External clock input pin of free-run timer 6 General-purpose input/output port
124
I/O
A
125
SIN7 AIN3 P18_5
I/O
A
Data input pin of USART7 Up/down counter input pin General-purpose input/output port
126
SOT7 BIN3
I/O
A
Data output pin of USART7 Up/down counter input pin (Continued)
DS07-16617-2E
11
MB91460S Series
(Continued) Pin no. 151 152 153 Pin name P23_6 INT11 P22_0 INT12 P22_2 INT13 P22_4 156 SDA0 INT14 157 P22_5 SCL0 P22_6 158 SDA1 INT15 159 P22_7 SCL1 P15_0 to P15_3 160 to 163 OCU0 to OCU3 TOT0 to TOT3 P14_0 to P14_7 ICU0 to ICU7 164 to 171 TIN8/0 to TIN 15/7 TTG24/16/8/0 to TTG31/23/15/7 172 to 175 P07_0 to P07_3 A0 to A3 I/O A I/O A I/O A I/O C I/O C I/O C I/O C I/O I/O I/O I/O I/O circuit type* A A A Function General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port I2C bus data input/output pin External interrupt input pin General-purpose input/output port I2C bus clock input/output pin General-purpose input/output port I2C bus data input/output pin External interrupt input pin General-purpose input/output port I2C bus clock input/output pin General-purpose input/output ports Output compare output pins Reload timer output pins General-purpose input/output ports Input capture input pins External trigger input pins of reload timer External trigger input pins of PPG timer General-purpose input/output ports Signal pins of external address bus (bit0 to bit3)
DS07-16617-2E
13
MB91460S Series
[Power supply/Ground pins] Pin no. Pin name 1, 23, 45, 67, 89, 94, 106, 111, 133, 155 66, 88, 110, 132, 154 108, 109 129 131 130 107 22, 44, 176 99, 105 104 VSS5 VDD5 VDD5R AVSS AVCC5 AVRH5 VCC18C VDD35 VSSA VDDA Supply
I/O Ground pins Power supply pins
Function
Power supply pins for internal regulator Analog ground pin for A/D converter Power supply pin for A/D converter Reference power supply pin for A/D converter Capacitor connection pin for internal regulator Power supply pins for external bus part of I/O ring Apixfi ground supply pins Apixfi power supply pin
* : For information about the I/O circuit type, refer to I/O CIRCUIT TYPES .
14
DS07-16617-2E
MB91460S Series
Type E Circuit
pull-up control driver strength control data line
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx.
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown
F
pull-up control driver strength control data line
pull- down control R CMOS hysteresis type1
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx. Analog input
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown analog input
DS07-16617-2E
17
MB91460S Series
Type J2
X1A R Xout
Circuit
Remarks Low-speed oscillation circuit: Feedback resistor = approx. 2 * 5 M . Feedback resistor is grounded in the center when the oscillator is disabled.
R X0A osc disable
K
pull-up control driver strength control data line
pull- down control R CMOS hysteresis type1
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx. LCD SEG/COM output
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown LCD SEG/COM
DS07-16617-2E
19
MB91460S Series
Type L Circuit
pull-up control driver strength control data line
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up resistor: 50k approx. Analog input LCD Voltage input
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown VLCD
M
tri-state control data line
CMOS level tri-state output (IOL = 5mA, IOH = -5mA)
N1/N2 Analog terminal Type N1: Analog input pin with protection Type N2: Analog output line with protection
analog line
20
DS07-16617-2E
MB91460S Series
HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5 or VDD35) or less than (VSS5) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
2. Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2K to 10K ) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS directly.
3. Power supply pins
In MB91460S series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the MB91460S series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between power supply pin and ground pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 F (use a X7R ceramic capacitor) to VCC18C pin for the regulator.
4. Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device.
5. Notes on using external clock 5.1. Opposite phase clock supply
When using the external clock, it is possible to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described combination X0 (X0A) should be supplied with a clock signal which has the opposite phase to the X1 (X1A) pins. However, in this case the stop mode (oscillation stop mode) must not be used (This is because the X1 (X1A) pin stops at H output in STOP mode). With opposite phase supply at X0 and X1, a frequency up to 16 MHz is possible.
DS07-16617-2E
21
MB91460S Series
Example of using opposite phase supply
X0 (X0A) X1 (X1A)
5.2.
Single phase clock supply
For lower frequencies, up to 4 MHz, it is possible to supply a single phase clock at X0 (X0A). Example of using single phase supply
X0 (X0A) X1 (X1A)
22
DS07-16617-2E
MB91460S Series
6. Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance. MD_3 pin should be connected directly to ground.
7. Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed.
8. Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
9. Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before and after the EIT always proceeds according to specification. 1) The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/ DIV0S instruction: (a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due to a data event or from the emulator menu. D0 and D1 flags are updated in advance. An EIT handling routine (user interrupt/NMI or emulator) is executed. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1).
2) The following behavior occurs when an ORCCR, STILM, MOV Ri, PS instruction is executed to enable a user interrupt or NMI source while that interrupt is in the active state. The PS register is updated in advance. An EIT handling routine (user interrupt/NMI or emulator) is executed. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1).
DS07-16617-2E
23
MB91460S Series
NOTES ON DEBUGGER
1. Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base timer interrupt handler). Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.
2. Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually contains data access instructions. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including an event breaks).
3. Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the areas containing the address of system stack pointer as a target of data event break.
24
DS07-16617-2E
MB91460S Series
4. Registers 4.1. General-purpose register
32 bits Initial value
R0 R1 ... ... R12 R13 R14 R15 AC FP SP ... ... XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2.
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always 0 . Write access to these bits is invalid. Bit position
bit 31 bit 20 bit 16 bit 10 bit 8 bit 7 bit 0
ILM
SCR
CCR
28
DS07-16617-2E
MB91460S Series
4.3. CCR (Condition Code Register)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
- 000XXXXB
SV
S
I
N
Z
V
C
SV : Supervisor flag S I Z V : Stack flag : Interrupt enable flag : Zero flag : Overflow flag
N : Negative enable flag
C : Carry flag
4.4.
SCR (System Condition Register)
bit 10 bit 9 bit 8
Initial value
XX0B
D1
D0
T
Flag for step multiplication (D1, D0) This flag stores interim data during execution of step multiplication. Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs.
4.5.
ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
01111B
ILM4 ILM3 ILM2 ILM1 ILM0
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value 01111B at reset.
4.6.
PC (Program Counter)
bit 31 bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined. DS07-16617-2E 29
MB91460S Series
3. Flash access in CPU mode 3.1. 3.1.1. Flash configuration Flash memory map MB91F467SA
Address 0014:FFFFh 0014:C000h 0014:BFFFh 0014:8000h 0014:7FFFh 0014:4000h 0014:3FFFh 0014:0000h 0013:FFFFh 0012:0000h 0011:FFFFh 0010:0000h 000F:FFFFh 000E:0000h 000D:FFFFh 000C:0000h 000B:FFFFh 000A:0000h 0009:FFFFh 0008:0000h 0007:FFFFh 0006:0000h 0005:FFFFh 0004:0000h addr+0 16bit read/write 32bit read/write 64bit read SA6 (8KB) SA7 (8KB)
SA4 (8KB)
SA5 (8KB) ROMS7
SA2 (8KB)
SA3 (8KB)
SA0 (8KB)
SA1 (8KB)
SA22 (64KB)
SA23 (64KB) ROMS6
SA20 (64KB)
SA21 (64KB)
SA18 (64KB)
SA19 (64KB)
ROMS5
SA16 (64KB)
SA17 (64KB)
ROMS4
SA14 (64KB)
SA15 (64KB)
ROMS3
SA12 (64KB)
SA13 (64KB)
ROMS2
SA10 (64KB)
SA11 (64KB)
ROMS1
SA8 (64KB) addr+1 addr+2 addr+3 addr+4
SA9 (64KB) addr+5 addr+6 addr+7
ROMS0
dat[31:16] dat[31:0]
dat[15:0]
dat[31:16] dat[31:0] dat[63:0]
dat[15:0]
32
DS07-16617-2E
MB91460S Series
3.2. Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) for Flash read and write access.
3.2.1.
Flash read timing settings (synchronous read)
ATD 0 0 1 1 ALEH 0 0 1 1 EQ 0 1 3 3 WEXH 0 0 0 0 WTC 1 2 4 4 Remark to 24 MHz to 48 MHz to 96 MHz to 100 MHz
Core clock (CLKB)
3.2.2.
Flash write timing settings (synchronous write)
ATD 1 1 1 1 1 ALEH 0 0 1 1 1 EQ 1 3 3 3 3 WEXH 0 0 0 0 0 WTC 4 5 6 7 7 Remark to 32 MHz to 48 MHz to 64 MHz to 96 MHz to 100 MHz
Core clock (CLKB)
3.3.
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel programming.
3.3.1.
Address mapping MB91F467SA
Flash sectors SA0, SA2, SA4, SA6 (8 Kbyte) SA1, SA3, SA5, SA7 (8 Kbyte) SA8, SA10, SA12, SA14, SA16, SA18, SA20, SA22 (64 Kbyte) SA9, SA11, SA13, SA15, SA17, SA19, SA21, SA23 (64 Kbyte) FA (flash address) Calculation FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h + 00:2000h FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0C:0000h FA := addr - addr%02:0000h + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0C:0000h + 01:0000h
CPU Address Condition (addr) 14:0000h to 14:FFFFh 14:0000h to 14:FFFFh 04:0000h to 13:FFFFh 04:0000h to 13:FFFFh addr[2]==0
addr[2]==1
addr[2]==0
addr[2]==1
Note: FA result is without 20:0000h offset for parallel Flash programming . Set offset by keeping FA[21] = 1 as described in section Parallel Flash programming mode .
DS07-16617-2E
33
MB91460S Series
4. Parallel Flash programming mode 4.1. Flash configuration in parallel Flash programming mode
MB91F467SA
FA[21:0] 003F:FFFFh 003F:0000h 003E:FFFFh 003E:0000h 003D:FFFFh 003D:0000h 003C:FFFFh 003C:0000h 003B:FFFFh 003B:0000h 003A:FFFFh 003A:0000h 0039:FFFFh 0039:0000h 0038:FFFFh 0038:0000h 0037:FFFFh 0037:0000h 0036:FFFFh 0036:0000h 0035:FFFFh 0035:0000h 0034:FFFFh 0034:0000h 0033:FFFFh 0033:0000h 0032:FFFFh 0032:0000h 0031:FFFFh 0031:0000h 0030:FFFFh 0030:0000h 002F:FFFFh 002F:E000h 002F:DFFFh 002F:C000h 002F:BFFFh 002F:A000h 002F:9FFFh 002F:8000h 002F:7FFFh 002F:6000h 002F:5FFFh 002F:4000h 002F:3FFFh 002F:2000h 002F:1FFFh 002F:0000h FA[1:0]=00 16bit write mode DQ[15:0] SA23 (64KB)
Parallel Flash programming mode (MD_[2:0] = 111):
SA22 (64KB)
SA21 (64KB)
SA20 (64KB)
SA19 (64KB)
SA18 (64KB)
SA17 (64KB)
SA16 (64KB)
SA15 (64KB)
SA14 (64KB)
SA13 (64KB)
SA12 (64KB)
SA11 (64KB)
SA10 (64KB)
SA9 (64KB)
SA8 (64KB)
SA7 (8KB)
SA6 (8KB)
SA5 (8KB)
SA4 (8KB)
SA3 (8KB)
SA2 (8KB)
SA1 (8KB)
SA0 (8KB) FA[1:0]=10 DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[21] = 1
34
DS07-16617-2E
MB91460S Series
5. Flash Security 5.1. Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection functions of the Flash Security Module: FSV1: 0x14:8000 BSV1: 0x14:8004 FSV2: 0x14:8008 BSV2: 0x14:800C
5.2.
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection of the 8 Kbytes sectors.
5.2.1.
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes. Explanation of the bits in the Flash Security Vector FSV1 [31:16] FSV1[18] FSV1[17] FSV1[16] Write Write Read FSV1[31:19] Protection Protection Protection Level set all to 0 set all to 0 set to 0 set to 0 set to 0 set to 1 set to 1 set to 0
Flash Security Mode Read Protection (all device modes, except INTVEC mode MD_[2:0] = 000 ) Write Protection (all device modes, without exception) Read Protection (all device modes, except INTVEC mode MD_[2:0] = 000 ) and Write Protection (all device modes) Read Protection (all device modes, except INTVEC mode MD_[2:0] = 000 ) Write Protection (all device modes, except INTVEC mode MD_[2:0] = 000 ) Read Protection (all device modes, except INTVEC mode MD_[2:0] = 000 ) and Write Protection (all device modes except INTVEC mode MD_[2:0] = 000 )
set all to 0
set to 0
set to 1
set to 1
set all to 0 set all to 0
set to 1 set to 1
set to 0 set to 1
set to 1 set to 0
set all to 0
set to 1
set to 1
set to 1
36
DS07-16617-2E
MB91460S Series
5.2.2. FSV1 (bit15 to bit0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set. Explanation of the bits in the Flash Security Vector FSV1 [15:0] Enable Write Disable Write FSV1 bit Sector Protection Protection FSV1[0] FSV1[1] FSV1[2] FSV1[3] FSV1[4] FSV1[5] FSV1[6] FSV1[7] FSV1[8] FSV1[9] FSV1[10] FSV1[11] FSV1[12] FSV1[13] FSV1[14] FSV1[15] SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 set to 1 set to 1 set to 1 set to 1 set to 1 set to 1 set to 1 set to 1 set to 1 set to 1 set to 1 not available not available not available not available not available not available not available not available set to 1 set to 1 set to 1 set to 1 Write protection is mandatory!
Comment
Note : It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash content or manipulate data by writing. See section Flash access in CPU mode for an overview about the sector organization of the Flash Memory.
DS07-16617-2E
37
MB91460S Series
APIX(R) CONTROLLER
1. Overview
The integrated APIXfi controller provides 2 links. Link 0 can be configured as an APIXfi link or an Automotive Interconnect (AIC) link. Link 1 only supports AIC link.
embedded PHY
SB ch down Pixel ch down
Link
AS 0
SB ch up
ARH
Downstream data Upstream data Downstream data Upstream data
AIC Link 0 AIC Link 1
AS 1
APIX(R) Controller
*Remark: Link 1 can be used only if Link 0 is activated (CHCTRL: TXCFG = 0)
APIX Link
Pixel Channel
Sideband Channel
downlink* Media: PHY -
downlink* PHY AIC
uplink PHY AIC AShell0 AShell0/1
*Remark: MB91460S series provides either downlink over Pixelchannel or over Sidebandchannel
DS07-16617-2E
39
MB91460S Series
2. Automotive Remote Handler
The Automotive Remote Handler provides an Interface to the APIXfi controller.
2.1. 2.1.1.
Register Description General Control
RHCTRL: Address 07200h
31 RHCTRL UNLOCK R0/W 23 R0 15 WDG1 R 7 R0 R0 R0 R 6 R0 WDG0 R 5 R0 R0 14 FAT1 R 4 R0 R0 13 FAT0 R0 3 R0 CANCEL R0/W 22 R0 12 R 2 R0 30 R0 21 R0 11 LV R 1 R0 20 R0 10 OFL R 0 29 28 TBNO[3] R/W 19 R0 9 EV 27 TBNO[2] R/W 18 R0 8 26 TBNO[1] R/W 17 25 TBNO[0] R/W 16 24
UNLOCK
0(def) 1
Transaction on buffer TBNO is requested Request unlock on waiting buffer TBNO Caution: Requested data gets lost or data is being received after using this buffer with same IDX
CANCEL TBNO[3:0] WDG1 WDG0 FAT0 FAT1 LV EV OFL
0(def) 1 0-15
Transaction on buffer TBNO is requested Request cancel on pending buffer TBNO Writing starts transaction on buffer number TBNO readonly flag of enabled and selected CHWDG1.WDTXIRQx or enabled and selected CHWDG1.WDRXIRQx readonly flag of enabled and selected CHWDG0.WDTXIRQx or enabled and selected CHWDG0.WDRXIRQx readonly flag of enabled CHCTRL0.FATIRQ readonly flag of enabled CHCTRL1.FATIRQ readonly flag of enabled EVCTRL.LVIRQ readonly flag of enabled EVCTRL.EVIRQ readonly flag of enabled EVCTRL.OFLIRQ
40
DS07-16617-2E
MB91460S Series
2.1.2. Channel Control and Status
CHCTRL0 (Link 0): Address 07208h CHCTRL1 (Link 1): Address 07214h
31 CHCTRL0-1 R0/WX 23 FATAL R 15 PLLGOOD R 7 RX/WX RX/WX UPRDY R 6 UPVALID R/(W) R 14 UPHSK R R0/WX 22 DNHSK RX/W 30 R0/WX 21 RX/W 29 reserved R/W0 20 RX/W 28 BYPASS R/W 19 27 R/W 18 FATIEN R/W 9 R/W 17 FATIRQ R(RM1)/W 8 REMOTERST R(RM1)/W 0 INITRH R/W 26 R/W 16 25 24
13 12 11 10 CONNECTED CRCERR CRCTOUT PERROR READY R R(RM1)/W R(RM1)/W R(RM1)/W R(RM1)/W 5 DNVALID R/(W) 4 R0 3 TXCFG R/W 2 RSTRTA R/W
1
Bit28 BYPASS: 0 1
reserved Bit Always write 0 to this bit. The read value is the value written. Remote Handler active Remote Handler inactive
In BYPASS mode Transaction Buffer 2 (for AShell 1) is used for downstream data (outbound) and Transaction Buffer 3 (for AShell 1) is used for upstream data (inbound). Valid written data in Transaction Buffer 0/2 is delivered to AShell by setting DNVALID. Valid received data in Transaction Buffer 1/3 from AShell is marked by setting UPVALID. FATAL UPHSK DNHSK FATIEN FATIRQ 1 1 1 0(def) 1 0(def) 1 indicates that AShell has encountered conditions where AShell can not continue to deliver and receive transactions. FATAL is only one CLKB cycle active. indicates inbound handshake is performed indicates outbound handshake is performed FATAL Interrupt disabled FATAL Interrupt enabled FATAL Interrupt not active FATAL Interrupt active, triggered by FATAL
*Remark: On a RMW instruction a 1 is read; write 0 clears the interrupt; write 1 is ignored *Remark: While Fatal Interrupt is active, the corresponding channel is deactivated and the triggered buffers are canceled. UPRDY CRCERR CRCTOUT PERROR DS07-16617-2E 1 1 1 1 indicates that upstream serial channel (APIXfi PHY) is operational a connection to remote APIXfi is established indicates occurrence of CRC error in upstream data (inbound) indicates occurrence of CRC timeout in upstream data (inbound) indicates occurrence of a protocol error 41 CONNECTED 1
*Remark: On a RMW instruction a 1 is read; write 0 clears the flag; write 1 is ignored *Remark: On a RMW instruction a 1 is read; write 0 clears the flag; write 1 is ignored
MB91460S Series
*Remark: On a RMW instruction a 1 is read; write 0 clears the flag; write 1 is ignored READY 1 indicates that AShell is ready to accept outbound transactions indicates a restart of remote AShell was performed read only Read only status (ap_data_out_valid) 0(def) Cleared by SW after successful reception (read) of upstream data 1 DNVALID BYPASS==0 BYPASS==1 TXCFG RSTRTA INITRH 0 1(def) 0 1(def) 0 1(def) Set by HW to mark upstream data as valid (ap_data_out_valid) read only DNVALID is only operational in BYPASS mode (always read 0) 0(def) Cleared by HW after successful transfer to AShell 1 Set by SW to mark downstream data as valid (ap_data_in_valid) AShell and PHY running (write protection on APCFG registers) AShell and PHY configuration (possible to change APCFG registers) AShell running Level AShell initialization Remote Handler running Level Remote Handler initialization (no change of TB* and TF* registers) REMOTERST 1 UPVALID BYPASS==0 BYPASS==1
*Remark: On a RMW instruction a 1 is read; write 0 clears the flag; write 1 is ignored
*Remark: PENDING requests (set while INIT==1) will be started with INIT==0 CHSTAT0 (Link 0): Address 0720Ch CHSTAT1 (Link 1): Address 07218h
31 CHSTAT0-1 R 23 R0 15 R 7 R R R 6 R R0 14 R 5 R R0 13 R R 22 R0 R 21 R0 12 UPSYNC[7:0] R 4 PLLBAD[7:0] R 11 R 3 R 2 R R 30 29 28 UPCRC[7:0] R 20 R0 10 R 1 R 27 R 19 R0 9 R 0 18 R0 8 26 R 17 25 R 16 24
UPCRC UPSYNC PLLBAD
0-255 0-255 0-255
Inbound CRC errors Synchronization losses PLL synchronization losses
42
DS07-16617-2E
MB91460S Series
2.1.3. Channel Watchdog
CHWDG0 (Link 0): Address 07210h CHWDG1 (Link 1): Address 0721Ch
CHWDG 31 30 WDTXIEN WDRXIEN R/W R/W R0 29 R0 28 WTTX1 R/W 27 WTTX0 R/W 26 WTRX1 R/W 25 WTRX0 R/W 24
23 22 21 20 19 18 17 16 WDTXIRQ3 WDTXIRQ2 WDTXIRQ1 WDTXIRQ0 WDRXIRQ3 WDRXIRQ2 WDRXIRQ1 WDRXIRQ0 R(RM1)/W R(RM1)/W R(RM1)/W R(RM1)/W R(RM1)/W R(RM1)/W R(RM1)/W R(RM1)/W 15 CNT19 R 7 CNT11 R R CNT10 R R 6 CNT9 R CNT18 R 5 CNT8 R 14 CNT17 R 4 CNT7 R 13 CNT16 R 3 CNT6 R 12 CNT15 R 2 CNT5 R 11 CNT14 R 1 CNT4 10 CNT13 R 0 9 CNT12 8
WDTXIEN WDRXIEN WTTX
0(def) 1 0(def) 1 0 1 2 3
Watchdog interrupt for TX is disabled Watchdog interrupt for TX is enabled Watchdog interrupt for RX is disabled Watchdog interrupt for RX is enabled select WDTXIRQ0 select WDTXIRQ1 select WDTXIRQ2 select WDTXIRQ3 select WDRXIRQ0 select WDRXIRQ1 select WDRXIRQ2 select WDRXIRQ3 interrupt for TX at 219 is not active interrupt for TX at 219 is active interrupt for TX at 216 is not active interrupt for TX at 216 is active interrupt for TX at 214 is not active interrupt for TX at 214 is active interrupt for TX at 213 is not active interrupt for TX at 213 is active interrupt for RX at 219 is not active interrupt for RX at 219 is active interrupt for RX at 218 is not active interrupt for RX at 218 is active interrupt for RX at 217 is not active interrupt for RX at 217 is active 43
WTRX
0 1 2 3
WDTXIRQ3 WDTXIRQ2 WDTXIRQ1 WDTXIRQ0 WDRXIRQ3 WDRXIRQ2 WDRXIRQ1
0(def) 1 0(def) 1 0(def) 1 0(def) 1 0(def) 1 0(def) 1 0(def) 1
DS07-16617-2E
MB91460S Series
SZ=Word
3
2
1
0 local
0
1
2
3 remote
SZ=Halfword
3
2
1
0 local
2
3
0
1 remote
TFIDX00 (Transaction Buffer 00): Address 07251h TFIDX01 (Transaction Buffer 01): Address 07253h TFIDX02 (Transaction Buffer 02): Address 07255h TFIDX03 (Transaction Buffer 03): Address 07257h TFIDX04 (Transaction Buffer 04): Address 07259h TFIDX05 (Transaction Buffer 05): Address 0725Bh TFIDX06 (Transaction Buffer 06): Address 0725Dh TFIDX07 (Transaction Buffer 07): Address 0725Fh TFIDX08 (Transaction Buffer 08): Address 07261h TFIDX09 (Transaction Buffer 09): Address 07263h TFIDX10 (Transaction Buffer 10): Address 07265h TFIDX11 (Transaction Buffer 11): Address 07267h TFIDX12 (Transaction Buffer 12): Address 07269h TFIDX13 (Transaction Buffer 13): Address 0726Bh TFIDX14 (Transaction Buffer 14): Address 0726Dh TFIDX15 (Transaction Buffer 15): Address 0726Fh
7 TFIDX00-15 IDX[7] R/W IDX[6] R/W 6 IDX[5] R/W 5 IDX[4] R/W 4 IDX[3] R/W 3 IDX[2] R/W 2 IDX[1] R/W 1 IDX[0] R/W 0
IDX[7:0]
Any number between 0 and 255
*Remark: Index is used for read request. Received data from a read request will be stored in an active Transaction Buffer with matching index. If there is no active Transaction Buffer with matching index (e.g. by using UNLOCK), the received data is discarded. TFADDR00 (Transaction Buffer 00): Address 07270h TFADDR01 (Transaction Buffer 01): Address 07274h TFADDR02 (Transaction Buffer 02): Address 07278h TFADDR03 (Transaction Buffer 03): Address 0727Ch TFADDR04 (Transaction Buffer 04): Address 07280h TFADDR05 (Transaction Buffer 05): Address 07284h TFADDR06 (Transaction Buffer 06): Address 07288h TFADDR07 (Transaction Buffer 07): Address 0728Ch TFADDR08 (Transaction Buffer 08): Address 07290h TFADDR09 (Transaction Buffer 09): Address 07294h TFADDR10 (Transaction Buffer 10): Address 07298h TFADDR11 (Transaction Buffer 11): Address 0729Ch DS07-16617-2E 47
MB91460S Series
TFADDR12 (Transaction Buffer 12): Address 072A0h TFADDR13 (Transaction Buffer 13): Address 072A4h TFADDR14 (Transaction Buffer 14): Address 072A8h TFADDR15 (Transaction Buffer 15): Address 072ACh
31 TFADDR00-15 R0 23 R0 R0 R0 -
30 R0 22 R0
29 R0 21 R0
28 R0 20
27 R0
26 R0
25 R0
24
19 18 17 16 ADDR[19] ADDR[18] ADDR[17] ADDR[16] R/W R/W R/W R/W
15 14 13 12 11 10 9 8 ADDR[15] ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] R/W R/W R/W R/W R/W R/W R/W R/W 7 ADDR[7] R/W ADDR[6] R/W 6 ADDR[5] R/W 5 ADDR[4] R/W 4 ADDR[3] R/W 3 ADDR[2] R/W 2 ADDR[1] R/W 1 ADDR[0] R/W 0
ADDR[19:0]
Address in remote system
TFDATA00 (Transaction Buffer 00): Address 072B0h TFDATA01 (Transaction Buffer 01): Address 072B4h TFDATA02 (Transaction Buffer 02): Address 072B8h TFDATA03 (Transaction Buffer 03): Address 072BCh TFDATA04 (Transaction Buffer 04): Address 072C0h TFDATA05 (Transaction Buffer 05): Address 072C4h TFDATA06 (Transaction Buffer 06): Address 072C8h TFDATA07 (Transaction Buffer 07): Address 072CCh TFDATA08 (Transaction Buffer 08): Address 072D0h TFDATA09 (Transaction Buffer 09): Address 072D4h TFDATA10 (Transaction Buffer 10): Address 072D8h TFDATA11 (Transaction Buffer 11): Address 072DCh TFDATA12 (Transaction Buffer 12): Address 072E0h TFDATA13 (Transaction Buffer 13): Address 072E4h TFDATA14 (Transaction Buffer 14): Address 072E8h TFDATA15 (Transaction Buffer 15): Address 076ECh
TFDATA00-15 31 30 29 28 27 26 25 24 DATA[31] DATA[30] DATA[29] DATA[28] DATA[27] DATA[26] DATA[25] DATA[24] R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 DATA[23] DATA[22] DATA[21] DATA[20] DATA[19] DATA[18] DATA[17] DATA[16] R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] R/W R/W R/W R/W R/W R/W R/W R/W 7 DATA[7] R/W DATA[6] R/W 6 DATA[5] R/W 5 DATA[4] R/W 4 DATA[3] R/W 3 DATA[2] R/W 2 DATA[1] R/W 1 DATA[0] R/W 0
DATA[31:0]
Payload data
48
DS07-16617-2E
MB91460S Series
2.1.7. Event Control
EVCTRL: Address 072F0h
31 EVCTRL reserved R/W0 23 MODE R/W 15 R 7 R/W R/W R 6 R/W R0 14 R 5 R/W R0 22 LVIEN R/W 13 R R0 21 LVIRQ R(RM1)/W 30 R0 20 OFLIEN R/W 11 R 3 R/W 2 R/W 29 R0 19 OFLIRQ R(RM1)/W 10 R 1 R/W 28 R0 18 EVIEN R/W 9 R 0 27 R0 17 EVIRQ R(RM1)/W 8 26 25 FRST R0/W 16 24
12 STATUS[7:0] R 4 LEVEL[7:0] R/W
Bit31 FRST MODE LVIEN LVIRQ 0(def) 1 0 (def) 1 0(def) 1 0(def) 1 OFLIEN OFLIRQ 0(def) 1 0(def) 1 EVIEN EVIRQ 0(def) 1 0(def) 1
reserved Bit Always write 0 to this bit. The read value is the value written. FIFO in normal operation FIFO pointers are reset pulse (set to 0 after 1 cycle) level mode On full FIFO new Events are discarded ring mode Level Interrupt disabled Level Interrupt enabled Level Interrupt not active Level Interrupt active (if STATUS>=LEVEL) Event Buffer Overflow Interrupt disabled Event Buffer Overflow Interrupt enabled Event Buffer Overflow Interrupt not active Event Buffer Overflow Interrupt active Event Buffer Interrupt disabled Event Buffer Interrupt enabled Event Buffer Interrupt not active Event Buffer Interrupt active
*Remark: On a RMW instruction a 1 is read; write 0 clears the interrupt; write 1 is ignored
*Remark: On a RMW instruction a 1 is read; write 0 clears the interrupt; write 1 is ignored
*Remark: On a RMW instruction a 1 is read; write 0 clears the interrupt; write 1 is ignored Set by hardware, reset by software STATUS[7:0] LEVEL[7:0] 0-128 0-128 Current FIFO filling status read only FIFO interrupt level (128 default)
DS07-16617-2E
49
MB91460S Series
2.1.8. Eventbuffer
EVBUF0: Address 072F8h EVBUF1: Address 072FCh
31 EVBUF0 R0 23 R/(W) 15 R0 7 R0 31 EVBUF1 R/(W) 23 R/(W) 15 R/(W) 7 R/(W) R/(W) R/(W) 6 R/(W) R/(W) 14 R/(W) 5 R/(W) 22 R/(W) 13 R/(W) 21 R/W 30 R/W 29 R0 6 R/W R0 5 R/W 27 R/(W) 19 R/(W) 11 R/(W) 3 R/(W) 2 R/(W) 10 R/(W) 1 R/(W) 18 R/(W) 9 R/(W) 0 R/(W) 14 R0 4 R/W 26 R/(W) 17 R/(W) 8 R0 22 R/(W) 13 R0 3 R/W 25 R/(W) 16 R0 21 R/(W) 30 R0 29 R0 20 EVIDX[7:0] R/(W) 12 R0 2 R/W 24 19 R/(W) 11 R/W 1 10 28 R0 18 R/(W) 9 reserved R/W0 0 27 R0 17 R/(W) 8 26 25 EVCH R/(W) 16 24
28 EVDATA0[7:0] R/(W) R/(W) 20 EVDATA1[7:0] R/(W) R/(W) 12 EVDATA2[7:0] R/(W) R/(W) 4 EVDATA3[7:0] R/(W) R/(W)
EVCH EVIDX[7:0] Bit8 EVDATA0-3
Holds channel number from Remote Handler RX event 0-255 Holds index number from Remote Handler RX event reserved Bit Always write 0 to this bit. The read value is the value written. 4 bytes of payload data
*Remark: It is recommended to read first EVBUF0 and A read access to EVBUF0 triggers a retrieve of the current event message from the event buffer fifo and returns the channel number and event index. A read access to EVBUF1 returns the data part of the a event message
50
DS07-16617-2E
MB91460S Series
2.1.9. Apix(R) configuration
APCFG0x (Link 0) APCFG1x (Link 1)
31 APCFG00/APCFG10 0 R/W 23 0 R/W 15 0 R/W 7 1 R/W R/W 0 R/W R/W 6 0 R/W 0 R/W 5 1 R/W R/W 14 0 R/W 0 R/W 13 0 R/W 4 config_byte_4 0 R/W 3 0 R/W R/W 22 1 R/W 0 R/W 21 1 R/W 12 config_byte_3 0 R/W 2 0 R/W 11 0 R/W 1 0 0 R/W 0 R/W 20 config_byte_2 0 R/W 10 0 R/W 0 19 0 R/W 9 0 30 29 28 config_byte_1 0 R/W 18 0 R/W 8 27 0 R/W 17 0 26 0 R/W 16 25 0 24
31 APCFG01/APCFG11 1 R/W 23 0 R/W 15 0 R/W 7 0 R/W R/W 1 R/W 0 R/W 0 R/W 1
30 1 R/W 22 0 R/W 14 0 R/W 6 0 R/W
29 1 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 config_byte_5 0 R/W 20 config_byte_6 0 R/W 12 config_byte_7 0 R/W 4 config_byte_8 1 R/W
27 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24
16
8
0
31 APCFG02/APCFG12 0 R/W 23 0 R/W 15 0 R/W 7 R/W R/W R/W 1 R/W 0 R/W 0
30 0 R/W 22 0 R/W 14 0 R/W 6 R/W
29 0 R/W 21
28 config_byte_9 0 R/W 20 config_byte_10 0 0 R/W 12 config_byte_11 0 0 R/W 4 R/W R/W -
27 0 R/W 19 0 R/W 11 0 R/W 3 R/W
26 1 R/W 18 1 R/W 10 0 R/W 2 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 R/W
24
16
R/W 13
8
R/W 5
0
31 APCFG03/APCFG13 0 R/W 23 1 R/W 15 1 R/W 7 0 R/W R/W 0 R/W 0 R/W 0 R/W 0
30 1 R/W 22 1 R/W 14 0 R/W 6 R/W
29
28 config_byte_shell_1 0 0 R/W R/W 20 config_byte_shell_2 0 0 R/W R/W 12 config_byte_shell_3 1 1 R/W R/W 4 config_byte_shell_4 R/W R/W
27 1 R/W 19 0/1 R/W 11 0 R/W 3 0 R/W
26 1 R/W 18 0 R/W 10 1 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24
21
16
13
8
5
0
AShell and PHY configuration.
DS07-16617-2E
51
MB91460S Series
2.1.10. Module ID
MODULEID: Address 07320h MODULEID[31:0]: Version of the APIXfi controller
3. APIX1/4(R) PHY Configuration 3.1. Powerdown
Configuration Vector: Bit Default APCFG 00 Description global power down (upstream, downstream and PLL) 1: power down 0: power up power down serializer and output driver (diff amp) 1: power down 0: power up power down upstream path 1: power down 0: power up
31
0
29
0
28
0
3.2.
Nominal Current
Configuration Vector: Bit 19 18 17 16 15 14 Default 0 0 0 0 0 0 000000: min (0 mA - power down output driver) 111111: max nominal current setting (64 steps) APCFG 01 Description
3.3.
Pre-emphasis
Configuration Vector: Bit 26 25 24 Default 0 0 0 pre-emphasis configuration: reduce output current (pre-emphasis) after N equal serial bits (N = 0..7) APCFG 00 Description
52
DS07-16617-2E
MB91460S Series
Configuration Vector: Bit 13 12 11 10 9 8 Default 0 0 0 0 0 0
APCFG 01 Description
pre-emphasis current setting (64 steps) 000000: min (0 mA - power down output driver) 111111: max
3.4.
Sampling Offset
Configuration Vector: Bit 11 10 9 8 Default 0 0 0 0 APCFG 00 Description upstream sampling point configuration 0000: optimum sampling point when operating in 62.50 Mbit/s mode 0010: optimum sampling point when operating in 41.67 Mbit/s or 31.25 Mbit/s mode 0100: optimum sampling point when operating in 20.83 Mbit/s mode
3.5.
Charge Pump Control
Configuration Vector: Bit 23 22 21 20 Default 1 0 0 0 charge pump current control APCFG 01 Description
DS07-16617-2E
53
MB91460S Series
4. DMA transfer request
To request a DMA transfer by a Transaction Buffer, please configure the transfer request source in DMACAx as follows. IS 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 EIS(DDNO) 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 RN
fi fi
Function APIX Transaction Buffer 0 APIX Transaction Buffer 1 APIXfi Transaction Buffer 2 APIXfi Transaction Buffer 3 APIX Transaction Buffer 4 APIX Transaction Buffer 5 APIXfi Transaction Buffer 6 APIXfi Transaction Buffer 7 APIX Transaction Buffer 8 APIX Transaction Buffer 9 APIXfi Transaction Buffer 10 APIXfi Transaction Buffer 11 APIX Transaction Buffer 12 APIX Transaction Buffer 13 APIXfi Transaction Buffer 14 APIXfi Transaction Buffer 15
fi fi fi fi fi fi
Transfer stop request available available available available available available available available available available available available available available available available
54
DS07-16617-2E
MB91460S Series
5. Automotive Interconnect Pins
The AIC Pins also serve as general ports. Pull-up Pull-down Standby control
Pin name
Pin function
I/O format
Setting required to use
Set port function mode
RCK0
AIC uplink clock of Apix(R) link0
PFR28: Bit0 = 1, EPFR28: Bit0 = 1 Set port function mode
RDA00 AIC uplink data of Apix(R) link0 RDA01
PFR28: Bit1 = 1, EPFR28: Bit1 = 1 Set port function mode PFR28: Bit2 = 1, EPFR28: Bit2 = 1 Set port function mode
TDA00 AIC downlink data of Apix(R) link0 TDA01
PFR28: Bit5 = 1, EPFR28: Bit5 = 1 Set port function mode PFR28: Bit6 = 1, EPFR28: Bit6 = 1 AIC downlink clock of Apix(R) link0 CMOS output and CMOS hysteresis, CMOS Automotive Programmable Provided hysteresis, TTL input Set port function mode PFR28: Bit7 = 1, EPFR28: Bit7 = 1 Set port function mode PFR17: Bit0 = 1, EPFR17: Bit0 = 1 Set port function mode
TCLI0
RCK1
AIC uplink clock of Apix(R) link1
RDA10 AIC uplink data of Apix(R) link1 RDA11
PFR17: Bit1 = 1, EPFR17: Bit1 = 1 Set port function mode PFR17: Bit2 = 1, EPFR17: Bit2 = 1 Set port function mode
TDA10 AIC downlink data of Apix(R) link1 TDA11
PFR17: Bit5 = 1, EPFR17: Bit5 = 1 Set port function mode PFR17: Bit6 = 1, EPFR17: Bit6 = 1 AIC downlink clock of Apix(R) link1 Set port function mode PFR17: Bit7 = 1, EPFR17: Bit7 = 1
TCLI1
DS07-16617-2E
55
MB91460S Series
6. USECASES 6.1. Communication over APIX(R) link
MB91F467SA
6.1.1. Downlink over Pixelchannel
APIX(R) RX
Downlink over Pixelchannel is provided by default configuration. Please configure the PHY according to Chapter APIX...fi PHY Configuration on page 52
6.1.2.
Downlink over Sidebandchannel
Bit 31 Default 1 Value 0 Description 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode
Register APCFG01
6.2. 6.2.1.
Communication over Automotive Interconnect to external AShell 1Bit Datawidth
D C
MB91F467SA
D C
embedded TX
APIX(R) RX
Register APCFGn1 APCFGn1 APCFGn3 APCFGn3
Bit 31 29 23 21
Default 1 1 1 1
Value 0 0 0 0
Description 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode 1: enable core clock of APIXfi PHY 0: disable 1: sbup_data[1:0] 0: sbup_data[0] 1: sbdown_data[1:0] 0: sbdown_data[0] AShell: connect internal Ashell to external APIXfi PHY through GPIO interface 1: enable 0: disable DS07-16617-2E
APCFGn3
18
0
1
56
MB91460S Series
6.2.2.
2Bit Datawidth
D[1:0] C
MB91F467SA
embedded TX
D [1:0] C
APIX(R) RX
Register APCFGn1 APCFGn1
Bit 31 29
Default 1 1
Value 0 0
Description 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode 1: enable core clock of APIXfi PHY 0: disable AShell: connect internal Ashell to external APIXfi PHY through GPIO interface 1: enable 0: disable
APCFGn3
18
0
1
6.3.
Communication over Automotive Interconnect to external PHY
DACL SBDOWN DATA[1] D SBDOWN DATA[0] INAP 125T24 / embedded TX
MB91F467SA
DACL SBUP_DATA[1] D SBUP_DATA[0]
APIX(R) RX
DS07-16617-2E
57
MB91460S Series
Register APCFGn1 APCFGn1
Bit 31 29
Default 1 1
Value 0 0
Description 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode 1: enable core clock of APIXfi PHY 0: disable AShell: validate sbup_data with 1: sbup_data[1] 0: sbup_valid AShell: generate sbdown clock and transmit as sbdown_data[1] 11: disable 10: with use of internal counter (asynchronous to core_clk of APIXfi PHY) 01: with use of sbdown_trigger (synchronous to core_clk of APIXfi PHY) 00: disable AShell: connect internal Ashell to external APIXfi PHY through GPIO interface 1: enable 0: disable AShell: configures cycle time of sbdown clock (multiples of Ashell core clock) when sbdown_data are asynchronous (sbdown_data[1] is used as sbdown clock) or cfg_spi_over_sb is enabled 0x0B: recommended minimum (no low bandwidth mode, AShell and APIXfi PHY operate at same core clock frequency) 0x14: recommended minimum (low bandwidth mode 2, AShell and APIXfi PHY operate at 62.5 MHz) 0x26: recommended minimum (low bandwidth mode 1, AShell and APIXfi PHY operate at 62.5 MHz)
APCFGn3 APCFGn3
22 20
0 0
1 1
APCFGn3
19
0
0
APCFGn3
18
0
1
2 1 0 30 APCFGn3 29 28 27 26 25 24
0 0 0 0 1 0 0 1 1 0 t.b.d.
6.4.
Caution
Up to now only the usecases Downlink over Pixelchannel on page 56 and Communication over Automotive Interconnect to external PHY on page 57 are guaranteed.
58
DS07-16617-2E
MB91460S Series
MEMORY SPACE
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH
DS07-16617-2E
59
MB91460S Series
MEMORY MAPS
1. MB91F467SA
MB91F467SA
00000000H 00000400H 00001000H 00002000H 00004000H 00006000H 00007000H 00008000H I/O (direct addressing area) I/O DMA
Flash-Cache (8 KBytes)
Flash memory control
0000B000H 0000C000H 0000D000H
Boot ROM (4 Kbytes) CAN
00028000H 00030000H 00038000H 00040000H
D-RAM (0 wait, 32 Kbytes) ID-RAM (32 Kbytes)
Flash memory (1088 Kbytes)
00150000H 00180000H External bus area 00500000H External data bus FFFFFFFFH
Note:
Access prohibited areas
60
DS07-16617-2E
MB91460S Series
I/O MAP
1. MB91F467SA
Address 000000H Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit port data register
Read/write attribute Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 1...) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.) Note : Initial values of register bits are represented as follows: 1 : Initial value 1 0 : Initial value 0 X : Initial value undefined - : No physical register at this location Access is barred with an undefined data access attribute.
DS07-16617-2E
61
MB91460S Series
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000024H to 00002CH 000030H 000034H 000038H 00003CH to 00004CH 000050H
Register +0 PDR00 [R/W] XXXXXXXX Reserved PDR08 [R/W] X - - X - - XX +1 PDR01 [R/W] XXXXXXXX PDR05 [R/W] XXXXXXXX PDR09 [R/W] - - - - XXXX +2 Reserved PDR06 [R/W] XXXXXXXX PDR10 [R/W] - - - - X - XX PDR14 [R/W] XXXXXXXX PDR18 [R/W] - XXX - XXX PDR22 [R/W] XXXX - X - X Reserved PDR29 [R/W] XXXXXXXX Reserved EIRR0 [R/W] XXXXXXXX EIRR1 [R/W] XXXXXXXX DICR [R/W] -------0 ENIR0 [R/W] 00000000 ENIR1 [R/W] 00000000 HRCL [R/W] 0 - - 11111 Reserved RDR02/TDR02 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 ELVR1 [R/W] 00000000 00000000 RBSYNC*1 Reserved PDR07 [R/W] XXXXXXXX Reserved PDR15 [R/W] - - - - XXXX PDR19 [R/W] - XXX - XXX PDR23 [R/W] - X - XXXXX +3
Block
Reserved PDR16 [R/W] XXXXXXXX PDR20 [R/W] - XXX - XXX PDR24 [R/W] XXXXXXXX PDR28 [R/W] XXXXXXXX PDR17 [R/W] XXXXXXXX Reserved
R-bus Port Data Register
External interrupt (INT 0 to INT 7) External interrupt (INT 8 to INT 15) Delay Interrupt
SCR02 [R/W, W] SMR02 [R/W, W] SSR02 [R/W, R] 00000000 00000000 00001000 ESCR02 [R/W] 00000X00 ECCR02 [R/W, R, W] -00000XX
LIN-USART 2
000054H
Reserved RDR03/TDR03 [R/W] 00000000
000058H
SCR03 [R/W, W] SMR03 [R/W, W] SSR03 [R/W, R] 00000000 00000000 00001000 ESCR03 [R/W] 00000X00 ECCR03 [R/W, R, W] -00000XX
LIN-USART 3
00005CH
Reserved (Continued)
62
DS07-16617-2E
MB91460S Series
Address
Register +0 +1 +2 +3 RDR04/TDR04 [R/W] 00000000 FCR04 [R/W] 0001 - 000 RDR05/TDR05 [R/W] 00000000 FCR05 [R/W] 0001 - 000 RDR06/TDR06 [R/W] 00000000 FCR06 [R/W] 0001 - 000 RDR07/TDR07 [R/W] 00000000 FCR07 [R/W] 0001 - 000
Block
000060H
SCR04 [R/W, W] SMR04 [R/W, W] SSR04 [R/W, R] 00000000 00000000 00001000 ESCR04 [R/W] 00000X00 ECCR04 [R/W, R, W] -00000XX FSR04 [R] - - - 00000
000064H
LIN-USART 4 with FIFO
000068H
SCR05 [R/W, W] SMR05 [R/W, W] SSR05 [R/W, R] 00000000 00000000 00001000 ESCR05 [R/W] 00000X00 ECCR05 [R/W, R, W] -00000XX FSR05 [R] - - - 00000
00006CH
LIN-USART 5 with FIFO
000070H
SCR06 [R/W, W] SMR06 [R/W, W] SSR06 [R/W, R] 00000000 00000000 00001000 ESCR06 [R/W] 00000X00 ECCR06 [R/W, R, W] -00000XX FSR06 [R] - - - 00000
000074H
LIN-USART 6 with FIFO
000078H
SCR07 [R/W, W] SMR07 [R/W, W] SSR07 [R/W, R] 00000000 00000000 00001000 ESCR07 [R/W] 00000X00 ECCR07 [R/W, R, W] -00000XX BGR002 [R/W] 00000000 BGR004 [R/W] 00000000 BGR006 [R/W] 00000000 FSR07 [R] - - - 00000
00007CH 000080H 000084H 000088H 00008CH 000090H to 0000CCH 0000D0H 0000D4H 0000D8H
LIN-USART 7 with FIFO
Reserved BGR102 [R/W] 00000000 BGR104 [R/W] 00000000 BGR106 [R/W] 00000000 BGR103 [R/W] 00000000 BGR105 [R/W] 00000000 BGR107 [R/W] 00000000 BGR003 [R/W] 00000000 BGR005 [R/W] 00000000 BGR007 [R/W] 00000000 Baud rate Generator LIN-USART 2 to 7
Reserved IBCR0 [R/W] 00000000 ITMKH0 [R/W] 00 - - - - 11 Reserved IBSR0 [R] 00000000 ITMKL0 [R/W] 11111111 IDAR0 [R/W] 00000000 ITBAH0 [R/W] - - - - - - 00 ISMK0 [R/W] 01111111 ICCR0 [R/W] - 0011111 ITBAL0 [R/W] 00000000 ISBA0 [R/W] - 0000000 Reserved (Continued) I2C 0
DS07-16617-2E
63
MB91460S Series
Address 0000DCH 0000E0H 0000E4H 0000E8H to 0000FCH 000100H 000104H 000108H 00010CH 000110H 000114H 000118H 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH
Register +0 IBCR1 [R/W] 00000000 ITMKH1 [R/W] 00 - - - - 11 Reserved +1 IBSR1 [R] 00000000 ITMKL1 [R/W] 11111111 IDAR1 [R/W] 00000000 +2 ITBAH1[R/W] - - - - - - 00 ISMK1 [R/W] 01111111 ICCR1 [R/W] - 0011111 +3 ITBAL1 [R/W] 00000000 ISBA1 [R/W] - 0000000 Reserved
Block
I2C 1
Reserved GCN10 [R/W] 00110010 00010000 GCN11 [R/W] 00110010 00010000 GCN12 [R/W] 00110010 00010000 PTMR00 [R] 11111111 11111111 PDUT00 [W] XXXXXXXX XXXXXXXX PTMR01 [R] 11111111 11111111 PDUT01 [W] XXXXXXXX XXXXXXXX PTMR02 [R] 11111111 11111111 PDUT02 [W] XXXXXXXX XXXXXXXX PTMR03 [R] 11111111 11111111 PDUT03 [W] XXXXXXXX XXXXXXXX PTMR04 [R] 11111111 11111111 PDUT04 [W] XXXXXXXX XXXXXXXX PTMR05 [R] 11111111 11111111 PDUT05 [W] XXXXXXXX XXXXXXXX GCN20 [R/W] - - - - 0000 GCN21 [R/W] - - - - 0000 GCN22 [R/W] - - - - 0000 PPG Control 0 to 3 PPG Control 4 to 7 PPG Control 8 to 11
Reserved Reserved Reserved Reserved
PCSR00 [W] XXXXXXXX XXXXXXXX PCNH00 [R/W] 0000000 PCNL00 [R/W] 000000 - 0
PPG 0
PCSR01 [W] XXXXXXXX XXXXXXXX PCNH01 [R/W] 0000000 PCNL01 [R/W] 000000 - 0
PPG 1
PCSR02 [W] XXXXXXXX XXXXXXXX PCNH02 [R/W] 0000000 PCNL02 [R/W] 000000 - 0
PPG2
PCSR03 [W] XXXXXXXX XXXXXXXX PCNH03 [R/W] 0000000 PCNL03 [R/W] 000000 - 0
PPG3
PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 PCNL04 [R/W] 000000 - 0
PPG 4
PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 PCNL05 [R/W] 000000 - 0
PPG 5
(Continued) 64 DS07-16617-2E
MB91460S Series
Address 000140H 000144H 000148H 00014CH 000150H 000154H 000158H 00015CH 000160H 000164H 000168H 00016CH
Register +0 +1 +2 +3 PTMR06 [R] 11111111 11111111 PDUT06 [W] XXXXXXXX XXXXXXXX PTMR07 [R] 11111111 11111111 PDUT07 [W] XXXXXXXX XXXXXXXX PTMR08 [R] 11111111 11111111 PDUT08 [W] XXXXXXXX XXXXXXXX PTMR09 [R] 11111111 11111111 PDUT09 [W] XXXXXXXX XXXXXXXX PTMR10 [R] 11111111 11111111 PDUT10 [W] XXXXXXXX XXXXXXXX PTMR11 [R] 11111111 11111111 PDUT11 [W] XXXXXXXX XXXXXXXX P0TMCSRH [R/W] - 0 - 000 - 0 P0TMCSRL [R/W] - - - 00000 PCSR06 [W] XXXXXXXX XXXXXXXX PCNH06 [R/W] 0000000 PCNL06 [R/W] 000000 - 0
Block
PPG 6
PCSR07 [W] XXXXXXXX XXXXXXXX PCNH07 [R/W] 0000000 PCNL07 [R/W] 000000 - 0
PPG 7
PCSR08 [W] XXXXXXXX XXXXXXXX PCNH08 [R/W] 0000000 PCNL08 [R/W] 000000 - 0
PPG 8
PCSR09 [W] XXXXXXXX XXXXXXXX PCNH09 [R/W] 0000000 PCNL09 [R/W] 000000 - 0
PPG 9
PCSR10 [W] XXXXXXXX XXXXXXXX PCNH10 [R/W] 0000000 PCNL10 [R/W] 000000 - 0
PPG 10
PCSR11 [W] XXXXXXXX XXXXXXXX PCNH11 [R/W] 0000000 P1TMCSRH [R/W] - 0 - 000 - 0 PCNL11 [R/W] 000000 - 0 P1TMCSRL [R/W] - - - 00000
PPG 11
000170H
000174H 000178H 00017CH 000180H 000184H 000188H
P0TMRLR [W] XXXXXXXX XXXXXXXX P1TMRLR [W] XXXXXXXX XXXXXXXX Reserved Reserved ICS01 [R/W] 00000000
P0TMR [R] XXXXXXXX XXXXXXXX P1TMR [R] XXXXXXXX XXXXXXXX ICS23 [R/W] 00000000
Pulse Frequency Modulator
Reserved
IPCP0 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX
IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX
Input Capture 0 to 3
(Continued)
DS07-16617-2E
65
MB91460S Series
Address 00018CH 000190H 000194H 000198H 00019CH 0001A0H 0001A4 0001A8H 0001ACH 0001B0H
Register +0 +1 +2 +3 OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX SGCRH [R/W] 0000 - - 00 SGAR [R/W] 00000000 SGCRL [R/W] - - 0 - - 000 Reserved OCS23 [R/W] - - - 0 - - 00 0000 - - 00 OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX SGFR [R/W, R] XXXXXXXX XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX
Block
Output Compare 0 to 3
Sound Generator
ADERH [R/W] 00000000 00000000 ADCS1 [R/W] 00000000 ADCT1 [R/W] 00010000 Reserved ADCS0 [R/W] 00000000 ADCT0 [R/W] 00101100 ACSR0 [R/W] - 11XXX00
ADERL [R/W] 00000000 00000000 ADCR1 [R] 000000XX ADSCH [R/W] - - - 00000 ADCR0 [R] XXXXXXXX ADECH [R/W] - - - 00000 Alarm Comparator 0 A/D Converter
Reserved TMR0 [R] XXXXXXXX XXXXXXXX TMCSRH0 [R/W] - - - 00000 TMCSRL0 [R/W] 0 - 000000
TMRLR0 [W] XXXXXXXX XXXXXXXX Reserved TMRLR1 [W] XXXXXXXX XXXXXXXX Reserved TMRLR2 [W] XXXXXXXX XXXXXXXX Reserved TMRLR3 [W] XXXXXXXX XXXXXXXX Reserved
Reload Timer 0 (PPG 0, PPG 1)
0001B4H
0001B8H
TMR1 [R] XXXXXXXX XXXXXXXX TMCSRH1 [R/W] - - - 00000 TMCSRL1 [R/W] 0 - 000000
Reload Timer 1 (PPG 2, PPG 3)
0001BCH
0001C0H
TMR2 [R] XXXXXXXX XXXXXXXX TMCSRH2 [R/W] - - - 00000 TMCSRL2 [R/W] 0 - 000000
Reload Timer 2 (PPG 4, PPG 5)
0001C4H
0001C8H
TMR3 [R] XXXXXXXX XXXXXXXX TMCSRH3 [R/W] - - - 00000 TMCSRL3 [R/W] 0 - 000000
Reload Timer 3 (PPG 6, PPG 7) (Continued)
0001CCH
66
DS07-16617-2E
MB91460S Series
Address 0001D0H
Register +0 +1 +2 +3 TMRLR4 [W] XXXXXXXX XXXXXXXX Reserved TMRLR5 [W] XXXXXXXX XXXXXXXX Reserved TMRLR6 [W] XXXXXXXX XXXXXXXX Reserved TMRLR7 [W] XXXXXXXX XXXXXXXX Reserved TMR4 [R] XXXXXXXX XXXXXXXX TMCSRH4 [R/W] - - - 00000 TMCSRL4 [R/W] 0 - 000000
Block
Reload Timer 4 (PPG 8, PPG 9)
0001D4H
0001D8H
TMR5 [R] XXXXXXXX XXXXXXXX TMCSRH5 [R/W] - - - 00000 TMCSRL5 [R/W] 0 - 000000
Reload Timer 5 (PPG 10, PPG 11)
0001DCH
0001E0H
TMR6 [R] XXXXXXXX XXXXXXXX TMCSRH6 [R/W] - - - 00000 TMCSRL6 [R/W] 0 - 000000
Reload Timer 6 (PPG 12, PPG 13)
0001E4H
0001E8H
TMR7 [R] XXXXXXXX XXXXXXXX TMCSRH7 [R/W] - - - 00000 TMCSRL7 [R/W] 0 - 000000 TCCS0 [R/W] 00000000
Reload Timer 7 (PPG 14, PPG 15) (A/D Converter) Free Running Timer 0 (ICU 0, ICU 1)
0001ECH
0001F0H
TCDT0 [R/W] XXXXXXXX XXXXXXXX
Reserved
0001F4H
TCDT1 [R/W] XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W] 00000000
Free Running Timer 1 (ICU 2, ICU 3)
0001F8H
TCDT2 [R/W] XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W] 00000000
Free Running Timer 2 (OCU 0, OCU 1)
0001FCH
TCDT3 [R/W] XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W] 00000000
Free Running Timer 3 (OCU 2, OCU 3) (Continued)
DS07-16617-2E
67
MB91460S Series
Address 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 0002CCH 0002D0H 0002D4H 0002D8H 0002DCH to 0002ECH
Register +0 +1 +2 +3 DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX Reserved DMACR [R/W] 00 - - 0000
Block
DMAC
Reserved
Reserved ICS045 [R/W] 00000000 ICS67 [R/W] 00000000 Input Capture 4 to 7
Reserved
Reserved
IPCP4 [R] XXXXXXXX XXXXXXXX IPCP6 [R] XXXXXXXX XXXXXXXX Reserved
IPCP5 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX
0002F0H
TCDT4 [R/W] XXXXXXXX XXXXXXXX
Reserved
TCCS4 [R/W] 00000000
Free Running Timer 4 (ICU 4, ICU 5) (Continued)
68
DS07-16617-2E
MB91460S Series
Address
Register +0 +1 +2 +3 TCCS5 [R/W] 00000000 TCCS6 [R/W] 00000000 TCCS7 [R/W] 00000000 UDCR0 [R] 00000000 UDCS0 [R/W] 00000000 UDCS1 [R/W] 00000000 UDCR2 [R] 00000000 UDCS2 [R/W] 00000000 UDCS3 [R/W] 00000000 GCN23 [R/W] - - - - 0000
Block Free Running Timer 5 (ICU 6, ICU 7)
0002F4H
TCDT5 [R/W] XXXXXXXX XXXXXXXX TCDT6 [R/W] XXXXXXXX XXXXXXXX TCDT7 [R/W] XXXXXXXX XXXXXXXX UDRC1 [W] 00000000 UDCCH0 [R/W] 00000000 UDCCH1 [R/W] 00000000 UDRC3 [W] 00000000 UDCCH2 [R/W] 00000000 UDCCH3 [R/W] 00000000 UDRC0 [W] 00000000 UDCCL0 [R/W] 00000000 UDCCL1[R/W] 00000000 UDRC2 [W] 00000000 UDCCL2 [R/W] 00000000 UDCCL3 [R/W] 00000000
Reserved
0002F8H 0002FCH 000300H 000304H 000308H 00030CH 000310H 000314H 000318H 00031CH 000320H 000324H to 00032CH 000330H 000334H 000338H 00033CH 000340H 000344H
Reserved Reserved UDCR1 [R] 00000000 Reserved Reserved
Free Running Timer 6 Free Running Timer 7
Up/Down Counter 0/1
Reserved UDCR3 [R] 00000000 Reserved Reserved
Up/Down Counter 2/3
Reserved GCN13 [R/W] 00110010 00010000 Reserved PPG Control 12 to 15
Reserved PTMR12 [R] 11111111 11111111 PDUT12 [W] XXXXXXXX XXXXXXXX PTMR13 [R] 11111111 11111111 PDUT13 [W] XXXXXXXX XXXXXXXX PTMR14 [R] 11111111 11111111 PDUT14 [W] XXXXXXXX XXXXXXXX PCSR12 [W] XXXXXXXX XXXXXXXX PCNH12 [R/W] 0000000 PCNL12 [R/W] 000000 - 0
PPG 12
PCSR13 [W] XXXXXXXX XXXXXXXX PCNH13 [R/W] 0000000 PCNL13 [R/W] 000000 - 0
PPG 13
PCSR14 [W] XXXXXXXX XXXXXXXX PCNH14 [R/W] 0000000 PCNL14 [R/W] 000000 - 0
PPG 14
(Continued)
DS07-16617-2E
69
MB91460S Series
Address 000348H 00034CH 000350H to 000364H 000368H 00036CH 000370H 000374H to 00038CH 000390H 000394H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H to 00043CH
Register +0 +1 +2 +3 PTMR15 [R] 11111111 11111111 PDUT15 [W] XXXXXXXX XXXXXXXX PCSR15 [W] XXXXXXXX XXXXXXXX PCNH15 [R/W] 0000000 Reserved IBCR2 [R/W] 00000000 ITMKH2 [R/W] 00 - - - - 11 Reserved IBSR2 [R] 00000000 ITMKL2 [R/W] 11111111 IDAR2 [R/W] 00000000 ITBAH2 [R/W] - - - - - - 00 ISMK2 [R/W] 01111111 ICCR2 [R/W] - 0011111 ITBAL2 [R/W] 00000000 ISBA2 [R/W] - 0000000 Reserved PCNL15 [R/W] 000000 - 0
Block
PPG 15
I2C 2
Reserved ROMS [R] 11111111 00000000 Reserved BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved (Continued)
Reserved
ROM Select Register
Bit Search Module
70
DS07-16617-2E
MB91460S Series
Address 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H 000474H 000478H 00047CH 000480H 000484H 000488H 00048CH 000490H
Register +0 ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111 ICR48 [R/W] ---11111 ICR52 [R/W] ---11111 ICR56 [R/W] ---11111 ICR60 [R/W] ---11111 RSRR [R/W] 10000000 CLKR [R/W] ---- 0000 PLLDIVM [R/W] - - - - 0000 PLLCTRL [R/W] - - - - 0000 +1 ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111 ICR49 [R/W] ---11111 ICR53 [R/W] ---11111 ICR57 [R/W] ---11111 ICR61 [R/W] ---11111 STCR [R/W] 00110011 WPR [W] XXXXXXXX PLLDIVN [R/W] - - 000000 +2 ICR02 [R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111 ICR50 [R/W] ---11111 ICR54 [R/W] ---11111 ICR58 [R/W] ---11111 ICR62 [R/W] ---11111 TBCR [R/W] 00XXX - 00 DIVR0 [R/W] 00000011 PLLDIVG [R/W] - - - - 0000 Reserved +3 ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111 ICR51 [R/W] ---11111 ICR55 [R/W] ---11111 ICR59 [R/W] ---11111 ICR63 [R/W] ---11111 CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 PLLDIVG [W] 00000000
Block
Interrupt Controller
Clock Control
Reserved
PLL Interface
(Continued) DS07-16617-2E 71
MB91460S Series
Address
Register +0 OSCC1 [R/W] - - - - - 010 PORTEN [R/W] - - - - - - 00 WTCER [R/W] - - - - - - 00 +1 OSCS1 [R/W] 00001111 +2 OSCC2 [R/W] - - - - - 010 Reserved Reserved Reserved Reserved WTHR [R/W] - - - 00000 CSVTR [R/W] - - - 00010 WTCR [R/W] 00000000 000 - 00 - 0 +3 OSCS2 [R/W] 00001111
Block Main/Sub Oscillator Control Port Input Enable Control
000494H
000498H 00049CH 0004A0H 0004A4H 0004A8H
WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] - - 000000 CSVCR [R/W] 00011100 WTSR [R/W] - - 000000 CSCFG [R/W] 0X000000 Reserved CMCFG [R/W] 00000000
Real Time Clock (Watch Timer)
0004ACH
ClockSupervisor / Selector / Monitor Calibration of Sub Clock
0004B0H 0004B4H 0004B8H 0004BCH 0004C0H 0004C4H 0004C8H
CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTR1 [R] - - - - - - - - 00000000 CMPR [R/W] - - 000010 11111101 CMT1 [R/W] 00000000 1 - - - 0000 CANPRE [R/W] - - 000000 LVSEL [R/W] 00000111 OSCRH [R/W] 000 - - 001 OSCCR [R/W] -------0 CANCKD [R/W] - - - - - - 00*3 LVDET [R/W] 0000 0 - 00 OSCRL [R/W] - - - - - 000
CUTD [R/W] 10000000 00000000 CUTR2 [R] 00000000 00000000 Reserved CMCR [R/W] - 001 - - 00
CMT2 [R/W] - - 000000 - - 000000 Reserved HWWDE [R/W] - - - - - - 00 WPCRH [R/W] 00 - - - 000 REGSEL [R/W] - - 000100
Clock Modulator
CAN Clock Control
HWWD [R/W, W] Low Voltage Detection/ 00011000 Hardware Watchdog WPCRL [R/W] - - - - - - 00 REGCTR [R/W] - - - 0 - - 00 Main-/Sub-Oscillation Stabilization Timer Main- Oscillation Standby Control Main-/Subregulator Control
0004CCH
Reserved
0004D0H to 00063CH
Reserved (Continued)
72
DS07-16617-2E
MB91460S Series
Address 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H 000688H to 0007F8H 0007FCH
Register +0 +1 +2 +3 ASR0 [R/W] 00000000 00000000 ASR1 [R/W] XXXXXXXX XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ASR3 [R/W] XXXXXXXX XXXXXXXX ASR4 [R/W] XXXXXXXX XXXXXXXX ASR5 [R/W] XXXXXXXX XXXXXXXX ASR6 [R/W] XXXXXXXX XXXXXXXX ASR7 [R/W] XXXXXXXX XXXXXXXX AWR0 [R/W] 01001111 11111011 AWR2 [R/W] XXXXXXXX XXXXXXXX AWR4 [R/W] XXXXXXXX XXXXXXXX AWR6 [R/W] XXXXXXXX XXXXXXXX MCRA [R/W] XXXXXXXX IORW0 [R/W] XXXXXXXX CSER [R/W] 00000001 RCRH [R/W] 00XXXXXX MCRB [R/W] XXXXXXXX Reserved IORW1 [R/W] XXXXXXXX CHER [R/W] 11111111 RCRL [R/W] XXXX0XXX Reserved MODR [W] XXXXXXXX IORW2 [R/W] XXXXXXXX Reserved ACR0 [R/W] 1111**00 00100000*4 ACR1 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX AWR1 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX Reserved
Block
External Bus
Reserved Reserved TCR [R/W] 0000**** *5
Reserved
Reserved
Reserved
Mode Register (Continued)
DS07-16617-2E
73
MB91460S Series
Address 000800H to 000CFCH 000D00H 000D04H 000D08H 000D0CH 000D10H 000D14H 000D18H 000D1CH 000D20H to 000D3CH 000D40H 000D44H 000D48H 000D4CH 000D50H 000D54H 000D58H 000D5CH 000D60H to 000D7CH 74
Register +0 +1 Reserved PDRD00 [R] XXXXXXXX Reserved PDRD08 [R] X - - X - - XX PDRD01 [R] XXXXXXXX PDRD05 [R] XXXXXXXX PDRD09 [R] - - - - XXXX +2 +3
Block
Reserved PDRD06 [R] XXXXXXXX PDRD10 [R] - - - - X - XX PDRD14 [R] XXXXXXXX PDRD18 [R] - XXX - XXX PDRD22 [R] XXXX - X - X PDRD07 [R] XXXXXXXX Reserved PDRD15 [R] - - - - XXXX PDRD19 [R] - XXX - XXX PDRD23 [R] -X - XXXXX R-bus Port Data Direct Read Register
Reserved PDRD16 [R] XXXXXXXX PDRD20 [R] - XXX - XXX PDRD24 [R] XXXXXXXX PDRD28 [R] XXXXXXXX PDRD17 [R] XXXXXXXX Reserved Reserved PDRD29 [R] XXXXXXXX
Reserved Reserved
Reserved DDR00 [R/W] 00000000 Reserved DDR08 [R/W] 0 - - 0 - -00 Reserved DDR16 [R/W] 00000000 DDR20 [R/W] - 000 - 000 DDR24 [R/W] 00000000 DDR28 [R/W] 00000000 DDR01 [R/W] 00000000 DDR05 [R/W] 00000000 DDR09 [R/W] - - - - 0000 Reserved DDR17 [R/W] 00000000 Reserved Reserved DDR29 [R/W] 00000000 Reserved (Continued) DS07-16617-2E
Reserved DDR06 [R/W] 00000000 DDR10 [R/W] - - - - 0 - 00 DDR14 [R/W] 00000000 DDR18 [R/W] - 000 - 000 DDR22 [R/W] 0000 - 0 - 0 Reserved DDR07 [R/W] 00000000 Reserved DDR15 [R/W] - - - - 0000 DDR19 [R/W] - 000 - 000 DDR23 [R/W] - 0 - 00000 Reserved R-bus Port Direction Register
Reserved
MB91460S Series
Address 000D80H 000D84H 000D88H 000D8CH 000D90H 000D94H 000D98H 000D9CH 000DA0H to 000DBCH 000DC0H 000DC4H 000DC8H 000DCCH 000DD0H 000DD4H 000DD8H 000DDCH 000DE0H to 000DFCH
Register +0 PFR00 [R/W] 00000000 Reserved PFR08 [R/W] 0 - - 0 - - 00 +1 PFR01 [R/W] 00000000 PFR05 [R/W] 00000000 PFR09 [R/W] - - - - 0000 +2 Reserved PFR06 [R/W] 00000000 PFR10 [R/W] - - - - 0 - 00 PFR14 [R/W] 00000000 PFR18 [R/W] - 000 - 000 PFR22 [R/W] 0000 - 0 - 0 Reserved PFR29 [R/W] 00000000 Reserved EPFR00 [R/W] -------Reserved EPFR08 [R/W] -------EPFR01 [R/W] -------EPFR05 [R/W] -------EPFR09 [R/W] -------Reserved PFR07 [R/W] 00000000 Reserved PFR15 [R/W] - - - - 0000 PFR19 [R/W] - 000 - 000 PFR23 [R/W] - 0 - 00000 +3
Block
Reserved PFR16 [R/W] 00000000 PFR20 [R/W] - 000 - 000 PFR24 [R/W] 00000000 PFR28 [R/W] 00000000 PFR17 [R/W] 00000000 Reserved
R-bus Port Function Register
Reserved EPFR06 [R/W] -------EPFR10 [R/W] -------0 EPFR14 [R/W] 00000000 EPFR18 [R/W] - 000 - 000 EPFR22 [R/W] -------Reserved EPFR07 [R/W] -------Reserved EPFR15 [R/W] - - - - 0000 EPFR19 [R/W] - 0- - - 0- EPFR23 [R/W] -------R-bus Extra Port Function Register
Reserved EPFR16 [R/W] 0000 - - - EPFR20 [R/W] - 000 - 000 EPFR24 [R/W] -------EPFR28 [R/W] - 000 - 000 EPFR29 [R/W] -------EPFR17 [R/W] - 000 - 000 Reserved
Reserved
Reserved (Continued)
DS07-16617-2E
75
MB91460S Series
Address 000E00H 000E04H 000E08H 000E0CH 000E10H 000E14H 000E18H 000E1CH 000E20H to 000E3CH 000E40H 000E44H 000E48H 000E4CH 000E50H 000E54H 000E58H 000E5CH 000E60H to 000E7CH
Register +0 PODR00 [R/W] 00000000 Reserved PODR08 [R/W] 0 - - 0 - - 00 +1 PODR01 [R/W] 00000000 PODR05 [R/W] 00000000 PODR09 [R/W] - - - - 0000 +2 Reserved PODR06 [R/W] 00000000 PODR10 [R/W] - - - - 0 - 00 PODR14 [R/W] 00000000 PODR18 [R/W] - 000 - 000 PODR22 [R/W] 0000 - 0 - 0 Reserved PODR29 [R/W] 00000000 Reserved PILR00 [R/W] 00000000 Reserved PILR08 [R/W] 0 - - 0 - - 00 PILR01 [R/W] 00000000 PILR05 [R/W] 00000000 PILR09 [R/W] - - - - 0000 Reserved PODR07 [R/W] 00000000 Reserved PODR15 [R/W] - - - - 0000 PODR19 [R/W] - 000 - 000 PODR23 [R/W] - 0 - 00000 +3
Block
Reserved PODR16 [R/W] 00000000 PODR20 [R/W] - 000 - 000 PODR24 [R/W] 00000000 PODR28 [R/W] 00000000 PODR17 [R/W] 0000 - - - Reserved
R-bus Port Output Drive Select Register
Reserved PILR06 [R/W] 00000000 PILR10 [R/W] - - - - 0 - 00 PILR14 [R/W] 00000000 PILR18 [R/W] - 000 - 000 PILR22 [R/W] 0000 - 0 - 0 Reserved PILR07 [R/W] 00000000 Reserved PILR15 [R/W] - - - - 0000 PILR19 [R/W] - 000 - 000 PILR23 [R/W] - 0 - 00000 R-bus Port Input Level Select Register
Reserved PILR16 [R/W] 00000000 PILR20 [R/W] - 000 - 000 PILR24 [R/W] 00000000 PILR28 [R/W] 00000000 PILR29 [R/W] 00000000 PILR17 [R/W] 0000 - - - Reserved
Reserved
Reserved (Continued)
76
DS07-16617-2E
MB91460S Series
Address 000E80H 000E84H 000E88H 000E8CH 000E90H 000E94H 000E98H 000E9CH 000EA0H to 000EBCH 000EC0H 000EC4H 000EC8H 000ECCH 000ED0H 000ED4H 000ED8H 000EDCH 000EE0H to 000EFCH
Register +0 EPILR00 [R/W] 00000000 Reserved EPILR08 [R/W] 0 - - 0 - - 00 +1 EPILR01 [R/W] 00000000 EPILR05 [R/W] 00000000 EPILR09 [R/W] - - - - 0000 +2 Reserved EPILR06 [R/W] 00000000 EPILR10 [R/W] - - - - 0 - 00 EPILR14 [R/W] 00000000 EPILR18 [R/W] - 000 - 000 EPILR22 [R/W] 0000 - 0 - 0 Reserved EPILR29 [R/W] 00000000 Reserved PPER00 [R/W] 00000000 Reserved PPER08 [R/W] 0 - - 0 - - 00 PPER01 [R/W] 00000000 PPER05 [R/W] 00000000 PPER09 [R/W] - - - - 0000 Reserved EPILR07 [R/W] 00000000 Reserved EPILR15 [R/W] - - - - 0000 EPILR19 [R/W] - 000 - 000 EPILR23 [R/W] - 0 - 00000 +3
Block
Reserved EPILR16 [R/W] 00000000 EPILR20 [R/W] - 000 - 000 EPILR24 [R/W] 00000000 EPILR28 [R/W] 00000000 EPILR17 [R/W] 0000 - - - Reserved
R-bus Extra Port Input Level Select Register
Reserved PPER06 [R/W] 00000000 PPER10 [R/W] - - - - 0 - 00 PPER14 [R/W] 00000000 PPER18 [R/W] - 000 - 000 PPER22 [R/W] 0000 - 0 - 0 Reserved PPER07 [R/W] 00000000 Reserved PPER15 [R/W] - - - - 0000 PPER19 [R/W] - 000 - 000 PPER23 [R/W] - 0 - 00000 R-bus Port Pull-Up/Down Enable Register
Reserved PPER16 [R/W] 00000000 PPER20 [R/W] - 000 - 000 PPER24 [R/W] 00000000 PPER28 [R/W] 00000000 PPER29 [R/W] 00000000 PPER17 [R/W] 0000 - - - Reserved
Reserved
Reserved (Continued)
DS07-16617-2E
77
MB91460S Series
Address 000F00H 000F04H 000F08H 000F0CH 000F10H 000F14H 000F18H 000F1CH 000F20H to 000F3CH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H
Register +0 PPCR00 [R/W] 11111111 Reserved PPCR08 [R/W] 1 - - 1- - 11 +1 PPCR01 [R/W] 11111111 PPCR05 [R/W] 11111111 PPCR09 [R/W] - - - - 1111 +2 Reserved PPCR06 [R/W] 11111111 PPCR10 [R/W] - - - - 1 - 11 PPCR14 [R/W] 11111111 PPCR18 [R/W] - 111 - 111 PPCR22 [R/W] 1111 - 1 - 1 Reserved PPCR29 [R/W] 11111111 Reserved DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved PPCR07 [R/W] 11111111 Reserved PPCR15 [R/W] - - - - 1111 PPCR19 [R/W] - 111 - 111 PPCR23 [R/W] - 1 - 11111 +3
Block
Reserved PPCR16 [R/W] 11111111 PPCR20 [R/W] - 111 - 111 PPCR24 [R/W] 11111111 PPCR28 [R/W] 11111111 PPCR17 [R/W] 11111111 Reserved
R-bus Port Pull-Up/Down Control Register
DMAC
(Continued)
78
DS07-16617-2E
MB91460S Series
Address 001028H to 001FFCH 002000H to 006FFCH 007000H 007004H 007008H 00700CH 007010H 007014H to 0071FCH 007200H 007204H 007208H 00720CH 007210H 007214H 007218H 00721CH
Register +0 +1 Reserved +2 +3
Block
MB91F467SA Flash-cache size is 8 Kbytes : 004000H to 005FFCH
Flash-cache / I-RAM area
FMCS [R/W] 01101000
FMCR [R] - - - 00000
FCHCR [R/W] - - - - - - 00 10000011 FMWT2 [R] - 001 - - - FMPS [R/W] - - - - - 000
FMWT [R/W] 11111111 11111111
FMAC [R] 00000000 00000000 00000000 00000000 FCHA0 [R/W] - - - - - - - - - - - 00000 00000000 00000000 FCHA1 [R/W] - - - - - - - - - - - 00000 00000000 00000000 Reserved RHCTRL[R/W] 00 - - 0000 - - - - - - - - 0000 - 000 - - - - - - - Reserved CHCTRL0[R/W] - - - - 0 - - - 000 - - - 00 00000000 - - 00 - - 000 CHSTAT0[R] 00000000 - - - - - - - - 00000000 00000000 CHWDG0[R/W] 00 - - 0000 00000000 xxxxxxxx xxxxxxxx CHCTRL1[R/W] - - - - 0 - - - 000 - - - 00 00000000 - - 00 - - 000 CHSTAT1[R] 00000000 - - - - - - - - 00000000 00000000 CHWDG1[R/W] 00 - - 0000 00000000 xxxxxxxx xxxxxxxx
Flash Memory/ Flash-cache/ I-RAM Control Register
Flash-cache Noncacheable area setting Register
Automotive Remote Handler Control
APIXfi Control/Status
(Continued)
DS07-16617-2E
79
MB91460S Series
Address 007220H 007224H 007228H 00722CH 007230H 007234H 007238H 00723CH 007240H 007244H to 00724CH 007250H 007254H 007258H 00725CH 007260H 007264H 007268H 00726CH 007270H 007274H
Register +0 +1 +2 +3 TBCTRL00[R/W] - - - 00000 0000 - 000 TBCTRL02[R/W] - - - 00000 0000 - 000 TBCTRL04[R/W] - - - 00000 0000 - 000 TBCTRL06[R/W] - - - 00000 0000 - 000 TBCTRL08[R/W] - - - 00000 0000 - 000 TBCTRL10[R/W] - - - 00000 0000 - 000 TBCTRL12[R/W] - - - 00000 0000 - 000 TBCTRL14[R/W] - - - 00000 0000 - 000 TBIRQ[R] 00000000 00000000 Reserved TFCRTL00[R/W] 00 - 00000 TFCRTL02[R/W] 00 - 00000 TFCRTL04[R/W] 00 - 00000 TFCRTL06[R/W] 00 - 00000 TFCRTL08[R/W] 00 - 00000 TFCRTL10[R/W] 00 - 00000 TFCRTL12[R/W] 00 - 00000 TFCRTL14[R/W] 00 - 00000 TFIDX00[R/W] 00000000 TFIDX02[R/W] 00000000 TFIDX04[R/W] 00000000 TFIDX06[R/W] 00000000 TFIDX08[R/W] 00000000 TFIDX10[R/W] 00000000 TFIDX12[R/W] 00000000 TFIDX14[R/W] 00000000 TFCRTL01[R/W] 00 - 00000 TFCRTL03[R/W] 00 - 00000 TFCRTL05[R/W] 00 - 00000 TFCRTL07[R/W] 00 - 00000 TFCRTL09[R/W] 00 - 00000 TFCRTL11[R/W] 00 - 00000 TFCRTL13[R/W] 00 - 00000 TFCRTL15[R/W] 00 - 00000 TFIDX01[R/W] 00000000 TFIDX03[R/W] 00000000 TFIDX05[R/W] 00000000 TFIDX07[R/W] 00000000 TFIDX09[R/W] 00000000 TFIDX11[R/W] 00000000 TFIDX13[R/W] 00000000 TFIDX15[R/W] 00000000 TBCTRL01[R/W] - - - 00000 0000 - 000 TBCTRL03[R/W] - - - 00000 0000 - 000 TBCTRL05[R/W] - - - 00000 0000 - 000 TBCTRL07[R/W] - - - 00000 0000 - 000 TBCTRL09[R/W] - - - 00000 0000 - 000 TBCTRL11[R/W] - - - 00000 0000 - 000 TBCTRL13[R/W] - - - 00000 0000 - 000 TBCTRL15[R/W] - - - 00000 0000 - 000 Reserved
Block
Automotive Remote Handler Transaction Buffer Control
Automotive Remote Handler Interrupt
Transaction Frame
TFADDR00[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR01[R/W] - - - - - - - - - - - - 0000 00000000 00000000 (Continued)
80
DS07-16617-2E
MB91460S Series
Address 007278H 00727CH 007280H 007284H 007288H 00728CH 007290H 007294H 007298H 00729CH 0072A0H 0072A4H 0072A8H 0072ACH 0072B0H 0072B4H 0072B8H 0072BCH 0072C0H 0072C4H 0072C8H
Register +0 +1 +2 +3 TFADDR02[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR03[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR04[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR05[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR06[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR07[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR08[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR09[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR10[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR11[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR12[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR13[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR14[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFADDR15[R/W] - - - - - - - - - - - - 0000 00000000 00000000 TFDATA00[R/W] 00000000 00000000 00000000 00000000 TFDATA01[R/W] 00000000 00000000 00000000 00000000 TFDATA02[R/W] 00000000 00000000 00000000 00000000 TFDATA03[R/W] 00000000 00000000 00000000 00000000 TFDATA04[R/W] 00000000 00000000 00000000 00000000 TFDATA05[R/W] 00000000 00000000 00000000 00000000 TFDATA06[R/W] 00000000 00000000 00000000 00000000
Block
(Continued) DS07-16617-2E 81
MB91460S Series
Address 0072CCH 0072D0H 0072D4H 0072D8H 0072DCH 0072E0H 0072E4H 0072E8H 0072ECH 0072F0H 0072F4H 0072F8H 0072FCH 007300H 007304H 007308H 00730CH 007310H 007314H 007318H 00731CH
Register +0 +1 +2 +3 TFDATA07[R/W] 00000000 00000000 00000000 00000000 TFDATA08[R/W] 00000000 00000000 00000000 00000000 TFDATA09[R/W] 00000000 00000000 00000000 00000000 TFDATA10[R/W] 00000000 00000000 00000000 00000000 TFDATA11[R/W] 00000000 00000000 00000000 00000000 TFDATA12[R/W] 00000000 00000000 00000000 00000000 TFDATA13[R/W] 00000000 00000000 00000000 00000000 TFDATA14[R/W] 00000000 00000000 00000000 00000000 TFDATA15[R/W] 00000000 00000000 00000000 00000000 EVCTRL[R/W] - - - - - - - 0 0 - 000000 00000000 00000000 Reserved EVBUF0[R/W] - - - - - - - 0 00000000 - - - - - - - - - - - - - - - EVBUF1[R/W] 00000000 00000000 00000000 00000000 APCFG00[R/W] 00000000 00110000 00000000 10010000 APCFG01[R/W] 11110000 10000000 00000000 01001000 APCFG02[R/W] 00000010 00000010 01000000 - - - - - - - APCFG03[R/W] 00100110 10100000 10011010 00 - - - 000 APCFG10[R/W] 00000000 00110000 00000000 10010000 APCFG11[R/W] 11110000 00000000 00000000 01001000 APCFG12[R/W] 00000010 00000010 01000000 - - - - - - - APCFG13[R/W] 00100110 10100100 10011010 00 - - - 000
Block
Automotive Remote Handler Eventcontrol
Automotive Remote Handler Eventqueue
APIXfi Configuration
(Continued) 82 DS07-16617-2E
MB91460S Series
Address 007320H 007324H to 007FFCH 008000H to 00BFFCH 00C000H 00C004H 00C008H 00C00CH 00C010H 00C014H 00C018H 00C01CH 00C020H 00C024H 00C028H, 00C02CH 00C030H 00C034H 00C038H, 00C03CH
Register +0 +1 +2 +3 MODULEID[R] 0 - - - - - - - ******** ******** ******** *6 Reserved
Block Version of APIXfi Controller
MB91F467SA Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH (instruction access is 1 wait cycle, data access is 1 wait cycle) CTRLR0 [R/W] 00000000 00000001 ERRCNT0 [R] 00000000 00000000 INTR0 [R] 00000000 00000000 BRPE0 [R/W] 00000000 00000000 IF1CREQ0 [R/W] 00000000 00000001 IF1MSK20 [R/W] 11111111 11111111 IF1ARB20 [R/W] 00000000 00000000 IF1MCTR0 [R/W] 00000000 00000000 IF1DTA10 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 Reserved IF1DTA20 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 Reserved IF1DTA10 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 STATR0 [R/W] 00000000 00000000 BTR0 [R/W] 00100011 00000001 TESTR0 [R/W] 00000000 X0000000 CBSYNC*2 IF1CMSK0 [R/W] 00000000 00000000 IF1MSK10 [R/W] 11111111 11111111 IF1ARB10 [R/W] 00000000 00000000 Reserved IF1DTA20 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000
Boot ROM area
CAN 0 Control Register
CAN 0 IF 1 Register
CAN 0 IF 1 Register
(Continued)
DS07-16617-2E
83
MB91460S Series
Address 00C040H 00C044H 00C048H 00C04CH 00C050H 00C054H 00C058H, 00C05CH 00C060H 00C064H 00C068H to 00C07CH 00C080H 00C084H to 00C08CH 00C090H 00C094H to 00C09CH 00C0A0H 00C0A4H to 00C0ACH 00C0B0H 00C0B4H to 00C0FCH
Register +0 +1 +2 +3 IF2CREQ0 [R/W] 00000000 00000001 IF2MSK20 [R/W] 11111111 11111111 IF2ARB20 [R/W] 00000000 00000000 IF2MCTR0 [R/W] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 Reserved IF2DTA20 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 Reserved TREQR20 [R] 00000000 00000000 Reserved NEWDT20 [R] 00000000 00000000 Reserved INTPND20 [R] 00000000 00000000 Reserved MSGVAL20 [R] 00000000 00000000 Reserved MSGVAL10 [R] 00000000 00000000 INTPND10 [R] 00000000 00000000 NEWDT10 [R] 00000000 00000000 TREQR10 [R] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 IF2CMSK0 [R/W] 00000000 00000000 IF2MSK10 [R/W] 11111111 11111111 IF2ARB10 [R/W] 00000000 00000000 Reserved IF2DTA20 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000
Block
CAN 0 IF 2 Register
CAN 0 Status Flags
(Continued) 84 DS07-16617-2E
MB91460S Series
Address 00C100H 00C104H 00C108H 00C10CH 00C110H 00C114H 00C118H 00C11CH 00C120H 00C124H 00C128H, 00C12CH 00C130H 00C134H 00C138H, 00C13CH
Register +0 +1 +2 +3 CTRLR1 [R/W] 00000000 00000001 ERRCNT1 [R] 00000000 00000000 INTR1 [R] 00000000 00000000 BRPE1 [R/W] 00000000 00000000 IF1CREQ1 [R/W] 00000000 00000001 IF1MSK21 [R/W] 11111111 11111111 IF1ARB21 [R/W] 00000000 00000000 IF1MCTR1 [R/W] 00000000 00000000 IF1DTA11 [R/W] 00000000 00000000 IF1DTB11 [R/W] 00000000 00000000 Reserved IF1DTA21 [R/W] 00000000 00000000 IF1DTB21 [R/W] 00000000 00000000 Reserved IF1DTA11 [R/W] 00000000 00000000 IF1DTB11 [R/W] 00000000 00000000 STATR1 [R/W] 00000000 00000000 BTR1 [R/W] 00100011 00000001 TESTR1 [R/W] 00000000 X0000000 Reserved IF1CMSK1 [R/W] 00000000 00000000 IF1MSK11 [R/W] 11111111 11111111 IF1ARB11 [R/W] 00000000 00000000 Reserved IF1DTA21 [R/W] 00000000 00000000 IF1DTB21 [R/W] 00000000 00000000
Block
CAN 1 Control Register
CAN 1 IF 1 Register
CAN 1 IF 1 Register
(Continued)
DS07-16617-2E
85
MB91460S Series
Address 00C140H 00C144H 00C148H 00C14CH 00C150H 00C154H 00C158H, 00C15CH 00C160H 00C164H 00C168H to 00C17CH 00C180H 00C184H to 00C18CH 00C190H 00C194H to 00C19CH 00C1A0H 00C1A4H to 00C1ACH 00C1B0H 00C1B4H to 00C1FCH
Register +0 +1 +2 +3 IF2CREQ1 [R/W] 00000000 00000001 IF2MSK21 [R/W] 11111111 11111111 IF2ARB21 [R/W] 00000000 00000000 IF2MCTR1 [R/W] 00000000 00000000 IF2DTA11 [R/W] 00000000 00000000 IF2DTB11 [R/W] 00000000 00000000 Reserved IF2DTA21 [R/W] 00000000 00000000 IF2DTB21 [R/W] 00000000 00000000 Reserved TREQR21 [R] 00000000 00000000 Reserved NEWDT21 [R] 00000000 00000000 Reserved INTPND21 [R] 00000000 00000000 Reserved MSGVAL21 [R] 00000000 00000000 Reserved MSGVAL11 [R] 00000000 00000000 INTPND11 [R] 00000000 00000000 NEWDT11 [R] 00000000 00000000 TREQR11 [R] 00000000 00000000 IF2DTA11 [R/W] 00000000 00000000 IF2DTB11 [R/W] 00000000 00000000 IF2CMSK1 [R/W] 00000000 00000000 IF2MSK11 [R/W] 11111111 11111111 IF2ARB11 [R/W] 00000000 00000000 Reserved IF2DTA21 [R/W] 00000000 00000000 IF2DTB21 [R/W] 00000000 00000000
Block
CAN 1 IF 2 Register
CAN 1 Status Flags
CAN 1 Status Flags
(Continued) 86 DS07-16617-2E
MB91460S Series
Address 00C200H to 00EFFCH 00F000H 00F004H 00F008H 00F00CH 00F010H 00F014H to 00F01CH 00F020H 00F024H 00F028H 00F02CH 00F030H to 00F07CH 00F080H 00F084H 00F088H 00F08CH 00F090H 00F094H 00F098H
Register +0 +1 Reserved BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000 BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000 +2 +3
Block
EDSU / MPU Reserved BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 Reserved BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued) EDSU / MPU
DS07-16617-2E
87
MB91460S Series
(Continued) Address 00F09CH 00F0A0H 00F0A4H 00F0A8H 00F0ACH 00F0B0H 00F0B4H 00F0B8H 00F0BCH 00F0C0H to 01FFFCH 020000H to 02FFFCH 030000H to 037FFCH 038000H to 03FFFCH Register +0 +1 +2 +3 BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved EDSU / MPU Block
MB91F467SA D-RAM size is 32 Kbytes : 028000H to 02FFFCH (data access is 0 wait cycles) MB91F467SA ID-RAM size is 32 Kbytes : 030000H to 037FFCH (instruction access is 0 wait cycles, data access is 1 wait cycle)
D-RAM area
ID-RAM area
Reserved
*1 : Use a read access ( byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt acceptance of the CPU) to a preceding write access to the resources on R-bus (e.g. to an interrupt flag) on following address (0x0000-0x01FF, 0x0280-0x037F, 0x0400-0x063F and 0x0C00-0x0FFF). *2 : Use a read access ( byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt acceptance of the CPU) to a preceding write access to the CANS on D-bus (e.g. to an interrupt flag) on following address (0x0000-0xFFFF). *3 : depends on the number of available CAN channels *4 : ACR0 [11 : 10] depends on Mode vector fetch information on bus width *5 : TCR [3 : 0] INIT value = 0000, keeps value after RST *6 : Datecode of APIXfi controller version
88
DS07-16617-2E
MB91460S Series
2. Flash memory and external bus area
dat[31:0] dat[31:16] +0 +1 +2 dat[15:0] + 3 Register +4 +5 + 6 +7 dat[31:0] dat[31:16] dat[15:0] Block
32bit write mode 16bit write mode Address 040000H to 05FFF8H 060000H to 07FFF8H 080000H to 09FFF8H 0A0000H to 0BFFF8H 0C0000H to 0DFFF8H 0E0000H to 0FFFF0H 0FFFF8H 100000H to 11FFF8H 120000H to 13FFF8H 140000H to 143FF8H 144000H to 17FF8H 148000H to 14BFF8H 14C000H to 14FFF8H 150000H to 17FFF8H DS07-16617-2E
SA8 (64kB)
SA9 (64kB)
ROMS0
SA10 (64kB)
SA11 (64kB)
ROMS1
SA12 (64kB)
SA13 (64kB)
ROMS2
SA14 (64kB)
SA15 (64kB)
ROMS3
SA16 (64kB)
SA17 (64kB)
ROMS4
SA18 (64kB) FMV [R] 06 00 00 00H SA20 (64kB)
SA19 (64kB) ROMS5 FRV [R] 00 00 BF F8H SA21 (64kB) ROMS6
SA22 (64kB)
SA23 (64kB)
SA0 (8kB)
SA1 (8kB)
SA2 (8kB)
SA3 (8kB)
SA4 (8kB)
SA5 (8kB)
ROMS7
SA6 (8kB)
SA7 (8kB)
Reserved (Continued) 89
MB91460S Series
(Continued) 32bit write mode 16bit write mode Address 180000H to 1BFFF8H 1C0000H to 1FFFF8H 200000H to 27FFF8H 280000H to 2FFFF8H 300000H to 37FFF8H 380000H to 3FFFF8H 400000H to 47FFF8H 480000H to 4FFFF8H dat[31:0] dat[31:16] +0 +1 +2 dat[15:0] + 3 Register +4 +5 + 6 +7 dat[31:0] dat[31:16] dat[15:0] Block
ROMS8
ROMS9
ROMS10
ROMS11 External Bus Area ROMS12
ROMS13
ROMS14
ROMS15
Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.
90
DS07-16617-2E
MB91460S Series
INTERRUPT VECTOR TABLE
Interrupt number Interrupt Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 440H 441H 442H 443H 444H 445H 446H Interrupt level*1 Interrupt vector*2 Default Vector address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H (Continued) DS07-16617-2E 91 0, 16 1, 17 2, 18 3, 19 20 21 22 23 DMA RN*5 Stop*6
Setting Register RegisOffset address ter 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H
Reset Mode vector System reserved System reserved System reserved CPU supervisor mode (INT #5 instruction) *7 Memory Protection exception *7 System reserved System reserved System reserved System reserved System reserved System reserved System reserved Undefined instruction exception NMI request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13
MB91460S Series
Interrupt number Interrupt Decimal 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Hexadecimal 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D
Interrupt level*1
Interrupt vector*2 Default Vector address 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H
DMA RN*5 Stop*6
Setting Register RegisOffset address ter ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 447H 448H 449H 44AH 44BH 44CH 44DH 44EH 44FH 450H 451H 452H 453H 454H 455H 456H 384H 380H 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H
External Interrupt 14 External Interrupt 15 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 4 Reload Timer 5 Reload Timer 6 Reload Timer 7 Free Run Timer 0 Free Run Timer 1 Free Run Timer 2 Free Run Timer 3 Free Run Timer 4 Free Run Timer 5 Free Run Timer 6 Free Run Timer 7 CAN 0 CAN 1 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved LIN-USART 2 RX LIN-USART 2 TX LIN-USART 3 RX LIN-USART 3 TX
4, 32 5, 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
6, 48 7, 49 8, 50 9, 51 52 53 54 55 (Continued)
92
DS07-16617-2E
MB91460S Series
Interrupt number Interrupt Decimal 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
4
Interrupt level*1
Interrupt vector*2 Default Vector address 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH 000FFEB8H 000FFEB4H 000FFEB0H 000FFEACH 000FFEA8H 000FFEA4H 000FFEA0H 000FFE9CH 000FFE98H 000FFE94H 000FFE90H 65 66 67
DMA RN*5 Stop*6
Hexadecimal 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B
Setting Register RegisOffset address ter ICR23 *3 (ICR24) ICR25 ICR26 ICR27 ICR28 ICR29 457H (458H) 459H 45AH 45BH 45CH 45DH 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H ICR31 45FH 2C4H 2C0H 2BCH 2B8H ICR33 ICR34 ICR35 ICR36 ICR37 461H 462H 463H 464H 465H 2B4H 2B0H 2ACH 2A8H 2A4H 2A0H 29CH 298H 294H 290H
System reserved Delayed Interrupt System reserved *4 System reserved * LIN-USART (FIFO) 4 RX LIN-USART (FIFO) 4 TX LIN-USART (FIFO) 5 RX LIN-USART (FIFO) 5 TX LIN-USART (FIFO) 6 RX LIN-USART (FIFO) 6 TX LIN-USART (FIFO) 7 RX LIN-USART (FIFO) 7 TX IC0/IC2 I2C 1 APIXfi Event/ Eventlevel/ Eventbufferoverflow/ Fatal Error/ Watchdog System reserved System reserved System reserved APIXfi Transaction Buffer System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved
2 2
10, 56 11, 57 12, 58 13, 59 60 61 62 63 28, 30 29
10, 56 12, 58 60 62 28, 30 29
ICR30
45EH
ICR32
460H
160175 69 70 71 72 73 74 75 76 77 78 79
160175
(Continued) DS07-16617-2E 93
MB91460S Series
Interrupt number Interrupt Decimal 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Hexadecimal 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B
Interrupt level*1
Interrupt vector*2 Default Vector address 000FFE8CH 000FFE88H 000FFE84H 000FFE80H 000FFE7CH 000FFE78H 000FFE74H 000FFE70H 000FFE6CH 000FFE68H 000FFE64H 000FFE60H 000FFE5CH 000FFE58H 000FFE54H 000FFE50H 000FFE4CH 000FFE48H 000FFE44H 000FFE40H 000FFE3CH 000FFE38H 000FFE34H 000FFE30H 000FFE2CH 000FFE28H 000FFE24H 000FFE20H 000FFE1CH 000FFE18H 000FFE14H 000FFE10H
DMA RN*5 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Stop*6
Setting Register RegisOffset address ter ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 *3 ICR48 ICR49 ICR50 ICR51 ICR52 ICR53 466H 467H 468H 469H 46AH 46BH 46CH 46DH 46EH 46FH 470H 471H 472H 473H 474H 475H 28CH 288H 284H 280H 27CH 278H 274H 270H 26CH 268H 264H 260H 25CH 258H 254H 250H 24CH 248H 244H 240H 23CH 238H 234H 230H 22CH 228H 224H 220H 21CH 218H 214H 210H
Input Capture 0 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Output Compare 0 Output Compare 1 Output Compare 2 Output Compare 3 System reserved System reserved System reserved System reserved Sound Generator Phase Frequency Modulator System reserved System reserved PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11
15, 96 97 98 99 100 101 102 103 104 105 106 107 (Continued)
94
DS07-16617-2E
MB91460S Series
(Continued) Interrupt number Interrupt Decimal 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 to 255 Hexadecimal 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 to FF Interrupt level*1 Interrupt vector*2 Default Vector address 000FFE0CH 000FFE08H 000FFE04H 000FFE00H 000FFDFCH 000FFDF8H 000FFDF4H 000FFDF0H 000FFDECH 000FFDE8H 000FFDE4H 000FFDE0H 000FFDDCH 000FFDD8H 000FFDD4H 000FFDD0H 000FFDCCH 000FFDC8H 000FFDC4H 000FFDC0H 000FFDBCH 000FFDB8H to 000FFC00H 14, 112 DMA RN*5 108 109 110 111 Stop*6
Setting Register RegisOffset address ter ICR54 ICR55 ICR56 ICR57 ICR58 ICR59 ICR60 ICR61 ICR62 ICR63 476H 477H 478H 479H 47AH 47BH 47CH 47DH 47EH 47FH 20CH 208H 204H 200H 1FCH 1F8H 1F4H 1F0H 1ECH 1E8H 1E4H 1E0H 1DCH 1D8H 1D4H 1D0H 1CCH 1C8H 1C4H 1C0H 1BCH 1B8H to 000H
PPG12 PPG13 PPG14 PPG15 Up/Down Counter 0 Up/Down Counter 1 Up/Down Counter 2 Up/Down Counter 3 Real Time Clock Calibration Unit A/D Converter 0 System reserved Alarm Comparator 0 System reserved Low Voltage Detection SMC Comparator 0 to 5 Timebase Overflow PLL Clock Gear DMA Controller Main/Sub OSC stability wait Security vector Used by the INT instruction.
*1 : The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. *3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]) *4 : Used by REALOS *5 :DMA RN is the resource number used for DMA operation. No number means that this resource interrupt cannot be used to trigger a DMA transfer. *6 :DMA Stop shows the DMA Transfer Stop Request feature. *7 :Memory Protection Unit (MPU) support DS07-16617-2E 95
MB91460S Series
RECOMMENDED SETTINGS
1. PLL and Clockgear settings
Please note that for MB91F467SA the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash. Recommended PLL divider and clockgear settings PLL Input (CLK) [MHz] 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Frequency Parameter DIVM 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 6 8 10 12 DIVN 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Clockgear Parameter DIVG 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 MULG 24 24 24 24 20 20 20 20 16 16 16 16 12 12 12 24 24 24 24 24 28 32 32 200 192 184 176 168 160 152 144 136 128 120 112 104 96 88 160 144 128 112 144 160 160 144 PLL Core Base Output (X) Clock [MHz] [MHz] MULG 100 96 92 88 84 80 76 72 68 64 60 56 52 48 44 40 36 32 28 24 20 16 12 Remarks
96
DS07-16617-2E
MB91460S Series
2. Clock Modulator settings
The clock modulator is currently being evaluated and should not be used for other purpose than testing. The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz. The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according to base clock frequency. Clock Modulator settings, frequency range and supported supply voltage Modulation Degree Random No CMPR Baseclk Fmin (k) (N) [hex] [MHz] [MHz] 1 1 1 1 2 1 1 1 2 3 1 1 1 2 3 1 1 1 1 2 2 3 4 1 1 1 1 1 2 DS07-16617-2E 3 3 3 5 3 3 5 7 3 3 3 5 7 3 3 3 5 7 9 3 5 3 3 3 5 7 9 11 3 026F 026F 026F 02AE 046E 026F 02AE 02ED 046E 066D 026F 02AE 02ED 046E 066D 026F 02AE 02ED 032C 046E 04AC 066D 086C 026F 02AE 02ED 032C 036B 046E 88 84 80 80 80 76 76 76 76 76 72 72 72 72 72 68 68 68 68 68 68 68 68 64 64 64 64 64 64 79.5 76.1 72.6 68.7 68.7 69.1 65.3 62 65.3 62 65.5 62 58.8 62 58.8 62 58.7 55.7 53 58.7 53 55.7 53 58.5 55.3 52.5 49.9 47.6 55.3
Fmax [MHz] 98.5 93.8 89.1 95.8 95.8 84.5 90.8 98.1 90.8 98.1 79.9 85.8 92.7 85.8 92.7 75.3 80.9 87.3 95 80.9 95 87.3 95 70.7 75.9 82 89.1 97.6 75.9
Remarks
(Continued) 97
MB91460S Series
Modulation Degree (k) 2 3 4 5 1 1 1 1 1 2 2 3 4 5 1 1 1 1 1 1 2 2 2 3 3 4 5 6 1 1 1 1 1 1 1
Random No (N) 5 3 3 3 3 5 7 9 11 3 5 3 3 3 3 5 7 9 11 13 3 5 7 3 5 3 3 3 3 5 7 9 11 13 15
CMPR [hex] 04AC 066D 086C 0A6B 026F 02AE 02ED 032C 036B 046E 04AC 066D 086C 0A6B 026F 02AE 02ED 032C 036B 03AA 046E 04AC 04EA 066D 06AA 086C 0A6B 0C6A 026F 02AE 02ED 032C 036B 03AA 03E9
Baseclk [MHz] 64 64 64 64 60 60 60 60 60 60 60 60 60 60 56 56 56 56 56 56 56 56 56 56 56 56 56 56 52 52 52 52 52 52 52
Fmin [MHz] 49.9 52.5 49.9 47.6 54.9 51.9 49.3 46.9 44.7 51.9 46.9 49.3 46.9 44.7 51.4 48.6 46.1 43.8 41.8 39.9 48.6 43.8 39.9 46.1 39.9 43.8 41.8 39.9 47.8 45.2 42.9 40.8 38.8 37.1 35.5
Fmax [MHz] 89.1 82 89.1 97.6 66.1 71 76.7 83.3 91.3 71 83.3 76.7 83.3 91.3 61.6 66.1 71.4 77.6 84.9 93.8 66.1 77.6 93.8 71.4 93.8 77.6 84.9 93.8 57 61.2 66.1 71.8 78.6 86.8 96.9
Remarks
(Continued) 98 DS07-16617-2E
MB91460S Series
Modulation Degree (k) 2 2 2 3 3 4 5 6 7 1 1 1 1 1 1 1 2 2 2 3 3 4 5 6 7 1 1 1 1 1 1 1 2 2 2
Random No (N) 3 5 7 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7
CMPR [hex] 046E 04AC 04EA 066D 06AA 086C 0A6B 0C6A 0E69 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 066D 06AA 086C 0A6B 0C6A 0E69 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA
Baseclk [MHz] 52 52 52 52 52 52 52 52 52 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 44 44 44 44 44 44 44 44 44 44
Fmin [MHz] 45.2 40.8 37.1 42.9 37.1 40.8 38.8 37.1 35.5 44.2 41.8 39.6 37.7 35.9 34.3 32.8 41.8 37.7 34.3 39.6 34.3 37.7 35.9 34.3 32.8 40.6 38.4 36.4 34.6 33 31.5 30.1 38.4 34.6 31.5
Fmax [MHz] 61.2 71.8 86.8 66.1 86.8 71.8 78.6 86.8 96.9 52.5 56.4 60.9 66.1 72.3 79.9 89.1 56.4 66.1 79.9 60.9 79.9 66.1 72.3 79.9 89.1 48.1 51.6 55.7 60.4 66.1 73 81.4 51.6 60.4 73
Remarks
(Continued) DS07-16617-2E 99
MB91460S Series
Modulation Degree (k) 2 3 3 4 4 5 6 7 8 1 1 1 1 1 1 1 2 2 2 2 3 3 3 4 4 5 6 7 8 9 1 1 1 1 1
Random No (N) 9 3 5 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7 9 3 5 7 3 5 3 3 3 3 3 3 5 7 9 11
CMPR [hex] 0528 066D 06AA 086C 08A8 0A6B 0C6A 0E69 1068 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 0528 066D 06AA 06E7 086C 08A8 0A6B 0C6A 0E69 1068 1267 026F 02AE 02ED 032C 036B
Baseclk [MHz] 44 44 44 44 44 44 44 44 44 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 36 36 36 36 36
Fmin [MHz] 28.9 36.4 31.5 34.6 28.9 33 31.5 30.1 28.9 37 34.9 33.1 31.5 30 28.7 27.4 34.9 31.5 28.7 26.3 33.1 28.7 25.3 31.5 26.3 30 28.7 27.4 26.3 25.3 33.3 31.5 29.9 28.4 27.1
Fmax [MHz] 92.1 55.7 73 60.4 92.1 66.1 73 81.4 92.1 43.6 46.8 50.5 54.8 59.9 66.1 73.7 46.8 54.8 66.1 83.3 50.5 66.1 95.8 54.8 83.3 59.9 66.1 73.7 83.3 95.8 39.2 42 45.3 49.2 53.8
Remarks
(Continued) 100 DS07-16617-2E
MB91460S Series
Modulation Degree (k) 1 1 2 2 2 2 3 3 3 4 4 5 6 7 8 9 1 1 1 1 1 1 1 2 2 2 2 2 3 3 3 4 4 5 5
Random No (N) 13 15 3 5 7 9 3 5 7 3 5 3 3 3 3 3 3 5 7 9 11 13 15 3 5 7 9 11 3 5 7 3 5 3 5
CMPR [hex] 03AA 03E9 046E 04AC 04EA 0528 066D 06AA 06E7 086C 08A8 0A6B 0C6A 0E69 1068 1267 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 0528 0566 066D 06AA 06E7 086C 08A8 0A6B 0AA6
Baseclk [MHz] 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Fmin [MHz] 25.8 24.7 31.5 28.4 25.8 23.7 29.9 25.8 22.8 28.4 23.7 27.1 25.8 24.7 23.7 22.8 29.7 28 26.6 25.3 24.1 23 22 28 25.3 23 21.1 19.5 26.6 23 20.3 25.3 21.1 24.1 19.5
Fmax [MHz] 59.3 66.1 42 49.2 59.3 74.7 45.3 59.3 85.8 49.2 74.7 53.8 59.3 66.1 74.7 85.8 34.7 37.3 40.2 43.6 47.7 52.5 58.6 37.3 43.6 52.5 66.1 89.1 40.2 52.5 75.9 43.6 66.1 47.7 89.1
Remarks
(Continued) DS07-16617-2E 101
MB91460S Series
(Continued) Modulation Degree (k) 6 7 8 9 10
Random No (N) 3 3 3 3 3
CMPR [hex] 0C6A 0E69 1068 1267 1466
Baseclk [MHz] 32 32 32 32 32
Fmin [MHz] 23 22 21.1 20.3 19.5
Fmax [MHz] 52.5 58.6 66.1 75.9 89.1
Remarks
102
DS07-16617-2E
MB91460S Series
2. Recommended operating conditions
(VSS5 = AVSS5 = 0.0 V) Parameter Symbol VDD5 VDD5R VDD35 Power supply voltage VDDA VPPA AVCC5 3.0 Value Min 3.0 3.0 3.0 1.7 Typ Max 5.5 5.5 5.5 1.9 50 5.5 Unit V V V V mV V Internal regulator External bus APIXfi VDDA, VSSA peak-peak supply noise A/D converter Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. Use a capacitor with a capacitance greater than Cs as the smoothing capacitor on the supply pin. Remarks
Smoothing capacitor
CS
4.7
F
Power supply slew rate Operating temperature Main Oscillation stabilization time Lock-up time PLL (4 MHz ->16 ...100MHz) ESD Protection (Human body model) RC Oscillator Vsurge fRC100kHz fRC2MHz 2 50 1 100 2 TA 40 10
50 + 105
V/ms C ms
0.6
ms kV Rdischarge = 1.5k Cdischarge = 100pF
200 4
kHz VDDCORE 1.65V MHz
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
DS07-16617-2E
105
MB91460S Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40 Parameter Symbol Input L voltage Pin name X0 4.5V VDD 5.5V, IOH = 2mA Normal outputs 3.0V VDD < 4.5V, IOH = 1.6mA 4.5V VDD 5.5V, Normal IOH = 5mA outputs 3.0V VDD < 4.5V, IOH = 3mA I2C 3.0V VDD 5.5V, outputs IOH = 3mA 4.5V VDD 5.5V, TA = -40 C, IOH = -40mA Condition Value Min VSS5 0.3 Typ Max 0.2 VDD Unit C to + 105 C) Remarks External clock in Fast Clock Input mode Driving strength set to 2 mA
VILXDF
V
VOH2
VDD
0.5
V
VOH5 Output H voltage
VDD
0.5
V
Driving strength set to 5 mA
VOH3
VDD
0.5
V
VOH30
High current 4.5V VDD 5.5V, outputs IOH = -30mA 3.0V VDD < 4.5V, IOH = -20mA 4.5V VDD 5.5V, Normal IOL = + 2mA outputs 3.0V VDD < 4.5V, IOL = + 1.6mA 4.5V VDD 5.5V, IOL = + 5mA Normal outputs 3.0V VDD < 4.5V, IOL = + 3mA I2C 3.0V VDD 5.5V, outputs IOL = + 3mA 4.5V VDD 5.5V, TA = -40 C, IOL = +40mA
VDD
0.5
V
Driving strength set to 30mA
VOL2
0.4
V
Driving strength set to 2 mA
VOL5 Output L voltage
0.4
V
Driving strength set to 5 mA
VOL3
0.4
V
VOL30
High current 4.5V VDD 5.5V, outputs IOL = +30mA 3.0V VDD < 4.5V, IOL = +20mA
0.5
V
Driving strength set to 30mA
(Continued)
108
DS07-16617-2E
MB91460S Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40 Parameter Symbol Pin name Condition Value Min 1 Typ Max +1 A 3 +3 Unit C to + 105 C) Remarks
Input leakage current
IIL
3.0V VDD 5.5V VSS5 < VI < VDD Pnn_m TA = 25 C *1 3.0V VDD 5.5V VSS5 < VI < VDD TA = 105 C 3.0V VDD AVSS5 VI TA = 25 C 5.5V AVCC5
Analog input leakage current
1
+1 A
IAIN
ADIN
3.0V VDD 5.5V AVSS5 VI AVCC5 TA = 105 C
3
+3
Sum input leakage
IL
VDD5 VIN VSS5 AVCC5, AVRH5 VIN AVSS5 Pnn_m (1 to n) [max (|ILALARM Hi|, |ILLi|)] (n = number of IO = 133 GPIO + 1 ALARM) Pnn_m 3.0V *1, INITX 4.5V Pnn_m 3.0V *1 4.5V SDINM SDINP SDOUTM SDOUTMP VDD VDD VDD VDD 3.6V 5.5V 3.6V 5.5V 40 25 40 25
13
130
A
Pull-up resistance Pull-down resistance
100 50 100 50
160 100 160 100 k
RUP
RDOWN
k
APIXfi terminal resistance
RTERM
35
65
(Continued)
DS07-16617-2E
109
MB91460S Series
(Continued) (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40 Parameter Symbol Pin name Condition Value Min Typ Max Unit C to + 105 C) Remarks (Conditions at MB91F467SA) CLKB: 100 MHz CLKP: 50 MHz CLKT: 50 MHz CLKCAN: 40 MHz Code fetch from Flash VDDA TA = + 25 C TA = + 105 C Power supply current VDD5R ICCH TA = + 25 C TA = + 105 C TA = + 25 C TA = + 105 C VDDA 12 30 400 100 500 50 450 10 60 150 2000 500 2400 250 2200 50 A A A A A A A APIXfi At stop mode *2 RTC : 4 MHz mode *2 RTC : 100 kHz mode *2 APIXfi powerdown External low voltage detection Internal low voltage detection Main clock (4 MHz) Sub clock (32 kHz)
ICC
VDD5R
125
155
mA
ILVE
VDD5
70
150
A
ILVI
VDD5R
50
100
A
250 IOSC VDD5 20 All except VDD5, VDD5R, VSS5, f = 1 MHz AVCC5, AVSS, VDDA, VSSA,
500 40
A A
Input capacitance
CIN
5
15
pF
*1 Pnn_m includes all pins unless the pins, which include analog inputs.
*2
Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled. DS07-16617-2E
110
MB91460S Series
4. A/D converter characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40 Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage VOT VFST ANn ANn 3 2.5 1.9 AVRL 1.5 LSB AVRH 3.5 LSB 1.0 Compare time Tcomp 2.0 s AVRL + 0.5 LSB AVRH 1.5 LSB Symbol Pin name Value Min Typ Max 10 +3 + 2.5 + 1.9 AVRL + 2.5 LSB AVRH + 0.5 LSB 16,500 Unit bit LSB LSB LSB V V s 4.5 V AV CC5 5.5 V 3.0 V AV CC5 < 4.5 V 4.5 V AV CC5 5.5 V, REXT < 2 k 3.0 V AV CC5 < 4.5 V, REXT < 1 k 4.5 V AV CC5 5.5 V 3.0 V AV CC5 < 4.5 V 4.5 V AV CC5 5.5 V 3.0 V AV CC5 < 4.5 V A A V LSB (Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller TA = + 25 C TA = + 105 C C to + 105 C) Remarks
0.4 Sampling time Tsamp 1.0
s
s
1.4 Conversion time Tconv 3.0 Input capacitance CIN ANn 11 2.6 Input resistance RIN ANn 12.1 Analog input leakage current Analog input voltage range Offset between input channels IAIN VAIN ANn ANn ANn 1 3 AVRL +1 +3 AVRH 4 k
s s pF k
DS07-16617-2E
111
MB91460S Series
(Continued) Parameter Symbol Pin name AVRH Reference voltage range AVRL IA IAH IR IRH AVSS5 AVCC5 AVCC5 AVRH5 AVRH5 0.7 AVRH5 Value Min 0.75 AVCC5 AVSS5 2.5 Typ Max AVCC5 AVCC5 0.25 5 5 1 5 Unit V V mA A mA A A/D Converter active A/D Converter not operated *1 A/D Converter active A/D Converter not operated *2 Remarks
Power supply current per ADC macro *3
Reference voltage current per ADC macro *3
*1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the current values have to be multiplied by the number of macros.
Sampling Time Calculation Tsamp = ( 2.6 kOhm + REXT) Tsamp = (12.1 kOhm + REXT) Conversion Time Calculation Tconv = Tsamp + Tcomp
11pF 7; for 4.5V AVCC5 5.5V 11pF 7; for 3.0V AV CC5 < 4.5V
Definition of A/D converter terms Resolution Analog variation that is recognizable by the A/D converter. Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B 00 0000 0001 B) and the full scale transition point (11 1111 1110B 11 1111 1111 B). Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error.
112
DS07-16617-2E
MB91460S Series
5. Alarm comparator characteristics
Parameter Symbol Pin name Value Min Typ Max Unit Remarks Alarm comparator enabled in fast mode (one channel) Alarm comparator enabled in fast mode (one channel) Alarm comparator disabled TA = + 25 C TA = + 105 C
IA5ALMF
25
40
A
Power supply current
AVCC5 IA5ALMS 7 10 A
IA5ALMH ALARM pin input current ALARM pin input voltage range Alarm upper limit voltage Alarm lower limit voltage Alarm hysteresis voltage Alarm input resistance Comparison time IALIN 1 3 0
5 +1 +3 AVCC5
A A
VALIN
V
VIAH
AVCC5 0.78 3% ALARM AVCC5 0.36 5%
AVCC5
0.78
AVCC5 0.78 + 3% AVCC5 0.36 + 5%
V
VIAL
AVCC5
0.36
V
VIAHYS
50
250
mV
RIN tCOMPF tCOMPS
5 0.1 1 0.2 2
M s s ACSR.MD=1 ACSR.MD=0
DS07-16617-2E
115
MB91460S Series
6. FLASH memory program/erase characteristics 6.1. MB91F467SA
Value Min 10 000 20 Typ 0.5 n*0.5 6 Max 2.0 n*2.0 100
(TA = 25oC, Vcc = 5.0V)
Parameter Sector erase time Chip erase time Word (16-bit width) programming time Programme/Erase cycle Flash data retention time Unit s s s cycle year *1 Remarks Erasure programming time not included n is the number of Flash sector of the device System overhead time not included
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC)
116
DS07-16617-2E
MB91460S Series
7. AC characteristics 7.1. Clock timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter Symbol Pin name X0 X1 X0A X1A Value Min 3.5 32 Typ 4 32.768 Max 16 100 Unit MHz kHz C to + 105 C)
Condition Opposite phase external supply or crystal
Clock frequency
fC
Clock timing condition
tC
X0, X1, X0A, X1A
PWH PWL
0.8 VCC 0.2 VCC
DS07-16617-2E
117
MB91460S Series
7.3. LIN-USART Timings at VDD5 = 3.0 to 5.5 V
Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = -40 C to +105 C - Cl = 50 pF (load capacity value of pins when testing) - VOL = 0.2 x VDD5, - VOH = 0.8 x VDD5 - EPILR = 0, PILR = 1 (Automotive Level = worst case) (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40 Parameter Serial clock cycle time SCK SOT delay time SOT SCK delay time Valid SIN SCK setup time SCK valid SIN hold time Serial clock H pulse width Serial clock L pulse width SCK SOT delay time Valid SIN SCK setup time SCK valid SIN hold time SCK rising time SCK falling time Symbol tSCYCI tSLOVI tOVSHI tIVSHI tSHIXI tSHSLE tSLSHE tSLOVE tIVSHE tSHIXE tFE tRE Pin name SCKn SCKn SOTn SCKn SOTn SCKn SINn SCKn SINn SCKn SCKn SCKn SOTn SCKn SINn SCKn SINn SCKn SCKn External clock operation (slave mode) Internal clock operation (master mode) Condition Min 4 tCLKP 30 m tCLKP 30* tCLKP + 55 0 tCLKP + 10 tCLKP + 10 2 tCLKP + 55 10 tCLKP + 10 20 20 10 tCLKP + 10 20 20 30 Max Min 4 tCLKP 20 m tCLKP 20* tCLKP + 45 0 tCLKP + 10 tCLKP + 10 2 tCLKP + 45 20 C to + 105 C) Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V
* : Parameter m depends on tSCYCI and can be calculated as : if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2 if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : The above values are AC characteristics for CLK synchronous mode. tCLKP is the cycle time of the peripheral clock.
DS07-16617-2E
119
MB91460S Series
Internal clock mode (master mode)
tSCYCI
SCKn for ESCR:SCES = 0
VOL
VOH
VOL
SCKn for ESCR:SCES = 1
VOH VOL
VOH
tSLOVI
tOVSHI VOH VOL tIVSHI VIH VIL
SOTn
tSHIXI VIH VIL
SINn
External clock mode (slave mode)
tSLSHE tSHSLE VOH VOL VOL VOL
SCKn for ESCR:SCES = 0
VOH
SCKn for ESCR:SCES = 1
VOL tFE
VOH
VOH tRE
VOL
VOH
tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL
SOTn
SINn
120
DS07-16617-2E
MB91460S Series
7.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V
Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = 40 C to + 105 C - Cl = 50 pF - VOL = 0.3 VDD5, VOH = 0.7 VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 VDD5/0.7 VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40 Parameter SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time for I2C-bus devices Data setup time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Pulse width of spike suppressed by input filter Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb tSP Pin name SCLn SCLn, SDAn SCLn SCLn SCLn, SDAn SCLn, SDAn SCLn SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn 0 Value Min 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 1.3 400 (1..1.5) tCLKP 300 300 0.9 Max 400 Unit kHz s s s s s ns ns ns s s pF ns *1 C to + 105 C) Remark
*1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock.
DS07-16617-2E
121
MB91460S Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH tCLASL
ASX
tCLAV
ADDRESS
DS07-16617-2E
125
MB91460S Series
7.7.2. Synchronous/Asynchronous read access
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter SYSCLK to RDX delay time setup time Symbol TCHRL TCHRH TDSRH TRHDX TCLWRL TCLWRH TCLCSL TCLCSH Pin name SYSCLK RDX RDX D31 to D16 RDX D31 to D16 SYSCLK WRXn SYSCLK CSXn Value Min 2 2 12 0 5 2 5 5 Max 5 5 C to + 105 C) Unit ns ns ns ns ns ns ns ns
Data valid to RDX RDX
to Data valid hold time
SYSCLK to WRXn (as byte enable) delay time SYSCLK to CSXn delay time
SYSCLK
tCLCSL tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn (as byte enable)
tCHRH tCHRL
RDX
tDSRH
tRHDX
DATA IN
126
DS07-16617-2E
MB91460S Series
7.7.4. Synchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter SYSCLK to WRXn delay time setup time Symbol TCLWRL TCLWRH TDSWRL TWRHDH TCLCSL TCLCSH Pin name SYSCLK WRXn WRXn D31 to D16 WRXn D31 to D16 SYSCLK CSXn Value Min 2 1 tCLKT 1 5 5 Max 5 C to + 105 C) Unit ns ns ns ns ns ns
Data valid to WRXn WRXn SYSCLK
to Data valid hold time to CSXn delay time
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRH tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
128
DS07-16617-2E
MB91460S Series
7.7.5. Asynchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter WEX to WEX pulse width setup time Symbol TWLWH TDSWL TWHDH TWRLWL TWHWRH TCLWL TWHCH Pin name WEX WEX D31 to D16 WEX D31 to D16 WEX WRXn WEX CSXn Value Min tCLKT 1 1/2 1/2 tCLKT 1 tCLKT 1 1/2 1/2 1/2 tCLKT 1 1/2 tCLKT 1 tCLKT + 1 tCLKT + 1 Max C to + 105 C) Unit ns ns ns ns ns ns ns
Data valid to WEX WEX
to Data valid hold time
WEX to WRXn delay time WEX to CSXn delay time
CSXn
tCLWL tWHCH
WRXn (as byte enable)
tWRLWL tWLWH tWHWRH
WEX
tDSWL
tWHDH
DATA OUT
DS07-16617-2E
129
MB91460S Series
7.7.7. RDY waitcycle insertion
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name SYSCLK RDY SYSCLK RDY Value Min 8 0 Max C to + 105 C) Unit ns ns
SYSCLK
tRDYS
tRDYH
RDY
DS07-16617-2E
131
MB91460S Series
7.8. External Bus AC Timings at VDD35 = 3.0 to 4.5 V
Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 3.0 V to 4.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = 40 C to + 105 C - Cl = 50 pF - VOL = 0.2 VDD35, VOH = 0.8 VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case)
7.8.1.
Basic Timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter Symbol TCLCH TCHCL to CSXn delay time TCLCSL TCLCSH TCHCSL TCLASL TCLASH TCLAV SYSCLK ASX SYSCLK A23 to A0 SYSCLK CSXn 2 Pin name SYSCLK Value Min 1/2 1/2 tCLKT tCLKT 2 1/2 1/2 7 6 6 7 13 Max tCLKT + 2 tCLKT 11 C to + 105 C) Unit ns ns ns ns ns ns ns ns
SYSCLK SYSCLK
SYSCLK to CSXn delay time (Addr CS delay) SYSCLK SYSCLK time to ASX delay time to Address valid delay
132
DS07-16617-2E
MB91460S Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH tCLASL
ASX
tCLAV
ADDRESS
DS07-16617-2E
133
MB91460S Series
7.8.2. Synchronous/Asynchronous read access
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter SYSCLK to RDX delay time setup time Symbol TCHRL TCHRH TDSRH TRHDX TCLWRL TCLWRH TCLCSL TCLCSH Pin name SYSCLK RDX RDX D31 to D16 RDX D31 to D16 SYSCLK WRXn SYSCLK CSXn Value Min 1 2 16 0 6 3 11 7 Max 4 6 C to + 105 C) Unit ns ns ns ns ns ns ns ns
Data valid to RDX RDX
to Data valid hold time
SYSCLK to WRXn (as byte enable) delay time SYSCLK to CSXn delay time
SYSCLK
tCLCSL tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn (as byte enable)
tCHRH tCHRL
RDX
tDSRH
tRHDX
DATA IN
134
DS07-16617-2E
MB91460S Series
7.8.5. Asynchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter WEX to WEX pulse width setup time Symbol TWLWH TDSWL TWHDH TWRLWL TWHWRH TCLWL TWHCH Pin name WEX WEX D31 to D16 WEX D31 to D16 WEX WRXn WEX CSXn 1/2 1/2 Value Min tCLKT tCLKT 7 tCLKT 3 1/2 1/2 1/2 tCLKT 1 1/2 tCLKT 1 tCLKT 1 tCLKT + 1 Max C to + 105 C) Unit ns ns ns ns ns ns ns
Data valid to WEX WEX
to Data valid hold time
WEX to WRXn delay time WEX to CSXn delay time
CSXn
TCLWL TWHCH
WRXn (as byte enable)
TWRLWL TWLWH TWHWRH
WEX
TDSWL
TWHDH
DATA OUT
DS07-16617-2E
137
MB91460S Series
7.8.6. Asynchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter WRXn to WRXn pulse width setup time Symbol TWRLWRH TDSWRL TWRHDH TCLWRL TWRHCH Pin name WRXn WRXn D31 to D16 WRXn D31 to D16 WRXn CSXn 1/2 1/2 Value Min tCLKT tCLKT 7 tCLKT 3 1/2 1/2 tCLKT 1 tCLKT+1 Max C to + 105 C) Unit ns ns ns ns ns
Data valid to WRXn WRXn
to Data valid hold time
WRXn to CSXn delay time
CSXn
TCLWRL TWRLWRH TWRHCH
WRXn
TDSWRL
TWRHDH
DATA OUT
138
DS07-16617-2E
MB91460S Series
7.8.7. RDY waitcycle insertion
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = 40 Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name SYSCLK RDY SYSCLK RDY Value Min 12 0 Max C to + 105 C) Unit ns ns
SYSCLK
tRDYS
tRDYH
RDY
DS07-16617-2E
139
MB91460S Series
ORDERING INFORMATION
Part number MB91F467SAPMC-GSE2 Package 176-pin plastic LQFP (FPT-176P-M07) Remarks Lead-free package
140
DS07-16617-2E
MB91460S Series
PACKAGE DIMENSION
176-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.50 mm 24.0 x 24.0 mm Gullwing Plastic mold 1.70 mm MAX P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP (FPT-176P-M07)
26.000.20(1.024.008)SQ *24.000.10(.945.004)SQ
Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
132
89
133
88
0.08(.003)
Details of "A" part 1.50 -0.10
+0.20 +.008
(Mounting height)
.059 -.004
0~8
0.100.10 (.004.004) (Stand off)
INDEX 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010)
176
45
"A" LEAD No.
1 44
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
(c)2004-2008 FUJITSU MICROELECTRONICS LIMITED F176013S-c-1-2 C
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/
DS07-16617-2E
141
MB91460S Series
MAIN CHANGES IN THIS EDITION
Page Section Preliminary Data Sheet The vertical lines marked in the left side of the page show the changes. Change Results Data Sheet
DS07-16617-2E
143
MB91460S Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

▲Up To Search▲

Price & Availability of MB91F467SAPMC-GSE2

	To Download MB91F467SAPMC-GSE2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .